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PDF HYB5117400BJ-50 Data sheet ( Hoja de datos )
| Número de pieza | HYB5117400BJ-50 | |
| Descripción | 4M x 4-Bit Dynamic RAM 2k & 4k Refresh | |
| Fabricantes | Siemens | |
| Logotipo |  |
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4M × 4-Bit Dynamic RAM
2k & 4k Refresh
(Fast Page Mode)
Advanced Information
• 4 194 304 words by 4-bit organization
• 0 to 70 °C operating temperature
• Fast Page Mode operation
• Performance:
tRAC RAS access time
tCAC CAS access time
tAA Access time from address
tRC Read/Write cycle time
tPC Fast page mode cycle time
-50 -60
50 60 ns
13 15 ns
25 30 ns
84 104 ns
35 40 ns
HYB 5116400BJ-50/-60
HYB 5117400BJ-50/-60
HYB 3116400BJ/BT-50/-60
HYB 3117400BJ-50/-60
• Power Dissipation, Refresh & Addressing:
Power Supply
Addressing
Refresh
Active
TTL Standby
CMOS Standby
HYB 5116400 HYB 3116400
-50 -60 -50 -60
5 V ± 10% 3.3 V ± 0.3 V
12/10
12/10
4096 cycles / 64 ms
275 220 180 144
11 7.2
5.5 3.6
HYB 5117400 HYB 3117400
-50 -60 -50 -60
5 V ± 10% 3.3 V ± 0.3 V
11/11
11/11
2048 cycles / 32 ms
440 385 288 252 mW
11 7.2 mW
5.5 3.6 mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package: P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
Semiconductor Group
1
1998-10-01
1 page  
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M × 4 DRAM
I/O1 I/O2 I/O3 I/O4
WE &
CAS
Data In
Buffer
4
Data Out
Buffer
OE
4
No.2 Clock
Generator
11 Column
Address
A0 Buffers (11)
A1
A2 Refresh
A3 Controller
A4
A5
A6 Refresh
A7 Counter (11)
A8
11
A9
A10 11 Row
Address
Buffers (11)
RAS
No.1 Clock
Generator
11 Column
Decoder
Sense Amplifier
I/O Gating
2048
x4
4
11
Row
Decoder
...
2048
...
Memory Array
2048 x 2048 x 4
Voltage Down
Generator
V CC
V CC (internal)
SPB02823
Block Diagram for HYB 5(3)117400 (2k-refresh)
Semiconductor Group
5
1998-10-01
5 Page 
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M × 4 DRAM
Notes
1. All voltages are referenced to VSS.
2. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once
or less during a fast page mode cycle (tPC).
5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS
cycles are required.
6. AC measurements assume tT = 5 ns.
7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times
are also measured between VIH and VIL.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as
a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is
controlled by tCAC.
10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as
a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is
controlled by tAA.
11.Either tRCH or tRRH must be satisfied for a read cycle.
12.tOFF (MAX.) and tOEZ (MAX.) define the time at which the outputs achieve the open-circuit condition
and are not referenced to output voltage levels.
13.Either tDZC or tDZO must be satisfied.
14.Either tCDD or tODD must be satisfied.
15.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle
and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if
tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD (MIN.) and tCPWD > tCPWD (MIN.), the cycle is a read-
write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets
of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
Semiconductor Group
11
1998-10-01
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet HYB5117400BJ-50.PDF ] | |
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