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PDF HYS72V32220GU-7-C2 Data sheet ( Hoja de datos )

Número de pieza HYS72V32220GU-7-C2
Descripción 3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules
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No Preview Available ! HYS72V32220GU-7-C2 Hoja de datos, Descripción, Manual

3.3V 16M x 64/72-Bit 1 BANK SDRAM Module
3.3V 32M x 64/72-Bit 2 BANK SDRAM Module
168 pin unbuffered DIMM Modules
HYS64/72V16300GU
HYS64/72V32220GU
168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
PC100 & PC133 versions
1 bank 16M x 64, 16M x 72 and 2 bank 132M x 64, 32M x 72 organisation
Optimized for byte-write non-parity (x64) or ECC (x72) applications
JEDEC standard Synchronous DRAMs (SDRAM)
Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
SDRAM Performance:
fCK Clock frequency (max.)
tAC Clock access time
Programmed Latencies :
-7.5
PC133
133
5.4
-8
PC100
100
6
mUnits
oMHz
cns
.
Product Speed
uCL
tRCD
tRP
-7.5 PC133
3
43 3
-8 PC100 2
t2 2
Single +3.3V(± 0.3V ) power supply
eProgrammable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
e
hAuto Refresh (CBR) and Self Refresh
sDecoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
aSerial Presence Detect with E2PROM
tUtilizes 16M x 8 SDRAMs in TSOPII-54 packages with 4096 refresh cycles every 64 ms
a133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads
d
.
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HYS72V32220GU-7-C2 pdf
HYS64(72)V16300/32220GU
SDRAM-Modules
CS1
CS0
DQMB0
DQ(7:0)
CS
DQM
DQ0-DQ7
D0
CS
DQM
DQ0-DQ7
D8
DQMB4
DQ(39:32)
CS
DQM
DQ0-DQ7
D4
CS
DQM
DQ0-DQ7
D12
DQMB1
DQ(15:8)
CS
DQM
DQ0-DQ7
D1
CS
DQM
DQ0-DQ7
D9
DQMB5
DQ(47:40)
CS
DQM
DQ0-DQ7
D5
CS
DQM
DQ0-DQ7
D13
CB(7:0)
CS3
CS2
DQMB2
DQ(23:16)
CS
DQM
DQ0-DQ7
D16
CS
DQM
DQ0-DQ7
D17
CS
DQM
DQ0-DQ7
D2
CS
DQM
DQ0-DQ7
D10
DQMB6
DQ(55:48)
CS
DQM
DQ0-DQ7
D6
CS
DQM
DQ0-DQ7
D14
DQMB3
DQ(31:24)
CS
DQM
DQ0-DQ7
D3
CS
DQM
DQ0-DQ7
D11
DQMB7
DQ(63:56)
CS
DQM
DQ0-DQ7
D7
CS
DQM
DQ0-DQ7
D15
A0-A11, BA0, BA1
D0-D15, (D16, D17)
VDD D0-D15, (D16, D17)
C0-C31, (C32...C35)
VSS D0-D7, (D8)
RAS, CAS, WE
D0-D15, (D16, D17)
E2PROM (256 Word x 8 Bit)
SA0 SA0
SA1 SA1 SDA
SA2 SA2 WP
SCL SCL
47 k
CKE0
CKE1
VDD
10 k
D0-D7, (D16)
D9-D15, (D17)
CLK0
CLK1
CLK2
CLK3
Clock Wiring
16 M x 64
16 M x 72
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 except otherwise noted. SPB03769
Block Diagram for 16M x 64/72 SDRAM DIMM modules (HYS64/72V1620GU)
INFINEON Technologies
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HYS72V32220GU-7-C2 arduino
HYS64(72)V16300/32220GU
SDRAM-Modules
SPD-Table for PC133 Modules:
Byte#
Description
SPD Entry Value
Hex
16Mx64 16Mx72 32Mx64 32Mx72
-7.5 -7.5 -7.5 -7.5
0 Number of SPD bytes
128
80
1 Total bytes in Serial PD
256
08
2 Memory Type
SDRAM
04
3 Number of Row Addresses
(without BS bits)
12
0C
4 Number of Column Addres-
ses(for 8Mx8 SDRAMs)
10
0A
5 Number of DIMM Banks
1/2
01
02
6 Module Data Width
64 / 72
40 48 40 48
7 Module Data Width (cont’d)
0
00
8 Module Interface Levels
LVTTL
01
9 SDRAM Cycle Time at CL=3
7.5 ns
75
10 SDRAM Access time from
Clock at CL=3
5.4 ns
54
11 Dimm Config
none / ECC 00 02 00 02
12 Refresh Rate/Type
Self-Refresh,
15.6µs
80
13 SDRAM width,Primary
x8
08
14 Error Checking SDRAM data
width
n/a / x8
00 08 00 08
15 Minimum clock delay for
back-to-back random column
address
tccd = 1 CLK
01
16 Burst Length supported
1, 2, 4 & 8
0F
17 Number of SDRAM banks
4
04
18 Supported CAS Latencies
CAS latency = 2
&3
06
19 CS Latencies
CS latency = 0
01
20 WE Latencies
Write latency = 0
01
21 SDRAM DIMM module
attributes
non buffered/non
reg.
00
22 SDRAM Device Attributes
:General
Vcc tol +/- 10%
0E
23 Min. Clock Cycle Time at
CAS Latency = 2
10.0 ns
A0
24 Max. data access time from
Clock for CL=2
6.0 ns
60
25 Minimum Clock Cycle Time
at CL = 1
not supported
FF
26 Maximum Data Access Time not supported
from Clock at CL=1
FF
27 Minimum Row Precharge
Time
20 ns
14
28 Minimum Row Active to Row
Active delay tRRD
15 ns
0F
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