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기능 DDR2 Registered Memory Modules
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HYS72T64000GR-37-A 데이터시트, 핀배열, 회로
Data Sheet, Rev. 0.85, Apr. 2004
HYS72T64000[G/H]R-x-A (512 MByte)
HYS72T128000[G/H]R-x-A (1 GByte)
HYS72T128020[G/H]R-x-A (1 GByte)
HYS72T256020[G/H]R-x-A (2 GByte)
HYS72T256220[G/H]R-x-A (2 GByte)
DDR2 Registered Memory Modules
Memory Products
Never stop thinking.




HYS72T64000GR-37-A pdf, 반도체, 판매, 대치품
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.3 Components on Modules and RawCard
DIMM
Density
DRAM components
reference datasheet
PLL
Register
Raw Card
512 MB
HYB18T512800AC
HYB18T512800AF
1:10, 1.8V, CU877 1:1 25-bit 1.8V SSTU32864
A
1024 MB
HYB18T512800AC
HYB18T512800AF
1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864
B
1024 MB
HYB18T512400AC
HYB18T512400AF
1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864
C
2048 MB
HYB18T512400AC
HYB18T512400AF
tbd.
tbd. tbd.
2048 MB
HYB18T512400AC
HYB18T512400AF
tbd.
tbd. tbd.
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data
sheet
1.4 Pin Definition and Function
Pin Name
Description
Pin Name
Description
A[13:0]
A11, A[9:0]
Row Address Inputs
Column Address Inputs 4)
CB[7:0]
DQS[8:0]
DIMM ECC Check Bits
SDRAM low data strobes
A10/AP
Column Address Input for Auto-
Precharge
DM[8:0] /
DQS[17:9]
SDRAM low data mask/
high data strobes
BA[1:0]
SDRAM Bank Selects
DQS[17:0]
SDRAM differential data strobes
CK0
Clock input
(positive line of differential pair)
SCL
Serial bus clock
CK0
Clock input
(negative line of differential pair)
SDA
Serial bus data line
RAS
Row Address Strobe
SA[2:0]
slave address select
CAS
WE
CS[1:0]
CKE[1:0]
ODT[1:0]
Column Address Strobe
Read/Write Input
Chip Selects 3)
Clock Enable 3)
Active termination control lines 1) 3)
VDD
VREF
VSS
VDDSPD
RESET
Power (+ 1.8 V)
I/O reference supply
Ground
EEPROM power supply
Register and PLL control pin 2)
DQ[63:0]
Data Input/Output
NC No connection
1) Active termination only applies to DQ, DQS, DQS and DM signals
2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the
PLL will remain synchronized with the input clock
3) CS1, ODT1 and CKE1 are used on dual rank modules only
4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
Data Sheet
Preliminary
4 Rev. 0.85, 2004-04

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HYS72T64000GR-37-A 전자부품, 판매, 대치품
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A
Registered DDR2 SDRAM Modules
1.7 Registered DIMM Input/Output Functional Description
Symbol
CK0, CK0
CKE[1:0]
CS[1:0]
Type
Input
Input
Input
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of
Cross point the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock.
CKE high activates and CKE low deactivates internal clock signals and device input buffers
Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).
Active Low
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations con-
tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on
the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except
CK, ODT and Chip select) remain in the previous state.
ODT[1:0]
RAS, CAS,
WE
Input
Input
Active High On-Die Termination control signals
Active Low
When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to
be executed by the SDRAM.
DM[8:0] Input Active High Masks write data when high, issued concurrently with input data.
BA[1:0] Input
A[13:0]
Input
DQ[63:0],
CB[7:0]
I/O
- Selects which internal SDRAM memory bank is activated
During Bank Activate command cycle, Address defines the row address. During a Read or
Write command cycle, Address defines the column address. In addition to the column
address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read
-
or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be
precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all
banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to
define which bank to precharge.
- Data and Check Bit Input /Output pins.
DQS[17:0],
DQS[17:0]
SA[2:0]
SDA
SCL
RESET
I/O
Input
I/O
Input
Input
The data strobes, associated with one data byte, source with data transfer. In Write mode,
the data strobe is sourced by the controller and is centered in the data window. In Read
mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the
Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of
respective DQS and DQS. If the module is to be operated in single ended strobe mode, all
DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
-
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial
SPD EEPROM address range
This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor
- maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pull-
up.
-
This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from
the SCL bus line to VDDSPD on the system planar to act as a pull-up.
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL.
- When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the
register(s) will be set to low level. The PLL will remain synchronized with the input clock.
VDD, VSS Supply - Power and ground for the DDR SDRAM input buffers and core logic.
VREF Supply - Reference voltage for the SSTL-18 inputs.
VDDSPD Supply
-
Serial EEPROM positive power supply, wired to a separated power pin at the connector
which supports from 1.7 Volt to 3.6 Volt.
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
Data Sheet
Preliminary
7 Rev. 0.85, 2004-04

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