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PDF HYS72V64220GU Data sheet ( Hoja de datos )

Número de pieza HYS72V64220GU
Descripción 3.3 V 64M x 64/72-Bit/ 512MByte SDRAM Modules 168-pin Unbuffered DIMM Modules
Fabricantes Infineon 
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HYS 64/72V64220GU
SDRAM-Modules
3.3 V 64M x 64/72-Bit, 512MByte SDRAM Modules
168-pin Unbuffered DIMM Modules
• 168-pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications using 256Mbit technology.
• PC100-222, PC133-333 & PC133-222
versions
• Two bank 64M × 64 and 64M × 72
organization
• Optimized for byte-write non-parity and ECC
applications
• JEDEC standard Synchronous DRAMs
(SDRAM)
• Programmed Latencies:
Product Speed
-7 PC133
-7.5 PC133
-8 PC100
CL tRCD
22
33
22
tRP
2
3
2
• Single + 3.3 V (± 0.3 V) power supply
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Uses Infineon 256 Mbit SDRAM components
in 32M × 8 organization and TSOPII-54
packages
• Fully PC board layout compatible to INTEL’s
Rev. 1.0 module specification
• Gold contact pad, card size:
133.35 mm × 31.75 mm × 4.00 mm
(JEDEC MO-161-BA)
• SDRAM Performance:
fCK Clock Frequency (max.)
tAC Clock Access time
-7
PC133
133
5.4
-7.5
PC133
133
5.4
-8
PC100
100
6
Unit
MHz
ns
Description
The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line
Memory Modules (DIMMs) which are organized as 64M × 64 and 64M × 72 in two banks high speed
memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC
applications. The DIMMs use “-7” speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet
the PC133-222 requirements, “-7.5” for PC133-333 and “-8” components for PC100-222
applications. Decoupling capacitors are mounted on the PC board. The PC board design is
according to INTEL’s module specification. The DIMMs have a serial presence detect, implemented
with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM
manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs
provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“
(31.75 mm) height.
INFINEON Technologies
1
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HYS72V64220GU pdf
HYS 64/72V64220GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Input / Output voltage relative to VSS
VIN, VOUT 1.0
4.6
Power supply voltage on VDD
VDD
1.0
4.6
Storage temperature range
TSTG
-55
+150
Power dissipation per SDRAM component
PD
1
Data out current (short circuit)
IOS
50
Permanent device damage may occur if Absolute Maximum Ratingsare exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Unit
V
V
oC
W
mA
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage (IOUT = 4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output Leakage Current
(DQ is disabled, 0 V < VOUT < VDD)
Symbol
Limit Values
min.
max.
VIH 2.0
VIL 0.5
VOH 2.4
VOL
II(L) 40
VDD + 0.3
0.8
0.4
40
Unit
V
V
V
V
µA
IO(L)
40
40
µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Input Capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)
Input Capacitance (CS0 - CS3)
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0, CKE1)
Input Capacitance (DQMB0 - DQMB7)
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
Input Capacitance (SCL, SA0-2)
Input/Output Capacitance
Symbol
CI1
Limit Values
max.
max.
64M × 64 64M × 72
105 144
Unit
pF
CI2 32 40 pF
CICL
40
43
pF
CI3 65 72 pF
CI4 20 25 pF
CIO 17 17 pF
CSC
8
8
pF
CSD
8
8
pF
INFINEON Technologies
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HYS72V64220GU arduino
HYS 64/72V64220GU
SDRAM-Modules
SPD-Table for 64M x 64 (512 MByte non-ECC) Modules HYS64V64220GU
Byte Description
#
34 SDRAM Data Input Hold Time
35 SDRAM Data Input Setup Time
36-61 Superset Information
62 SPD Revision
63 Checksum for Bytes 0 - 62
64 Manufacturers JEDEC ID Code
65-71 Manufacturer
72 Module Assembly Locaction
73-90 Module Part Number
91-92 Module Revision Code
93-94 Module Manufacturing Code
95-98 Module Serial Number
99- Superset Information
125
126 Frequency Specification
127 100 MHz Support Details
128+ Unused Storage Locations
SPD Entry Value
1.5 / 2.0 ns
0.8 / 1.0 ns
Revision 1.2
Hex
64M x 64
-7 -7.5 -8
15 15 20
08 08 10
FF FF FF
12 12 12
F4 37 9A
C1
INFINEO(N)
64 64 64
FF FF FF
FF FF FF
INFINEON Technologies
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