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PDF HYS72V8200GU-10 Data sheet ( Hoja de datos )
| Número de pieza | HYS72V8200GU-10 | |
| Descripción | 3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module | |
| Fabricantes | Siemens | |
| Logotipo |  |
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3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module
3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module
168 pin unbuffered DIMM Modules
HYS 64/72V8200GU
HYS 64/72V16220GU
• 168 Pin PC100-compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
• 1 bank 8M × 64, 8M × 72 and 2 bank 16M × 64, 16M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• JEDEC standard Synchronous DRAMs (SDRAM)
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• SDRAM Performance
fCK Clock frequency (max.)
tAC Clock access time
• Programmed Latencies
-8 -8B -10 Units
100 100
66 MHz
6 6 8 ns
Product Speed
-8 PC100
-8B PC100
-10 PC66
CL
2
3
2
tRCD
2
2
2
tRP
2
3
2
• Single + 3.3 V (± 0.3 V ) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 8M × 8 SDRAMs in TSOPII-54 packages
• 4096 refresh cycles every 64 ms
• 133.35 mm × 31.75 mm × 4.00 mm card size with gold contact pads
Semiconductor Group
1
1998-08-01
1 page  
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
WE
CS0
DQMB0
DQ(7:0)
CS WE
DQM
DQ0-DQ7
D0
DQMB1
DQ(15:8)
CS WE
DQM
DQ0-DQ7
D1
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS WE
DQM
DQ0-DQ7
D8
CS WE
DQM
DQ0-DQ7
D2
DQMB3
DQ(31:24)
CS WE
DQM
DQ0-DQ7
D3
A0-A11, BA0, BA1
D0-D7, (D8)
VCC D0-D7, (D8)
C0-C15, (C16, C17)
VSS D0-D7, (D8)
RAS D0-D7, (D8)
CAS D0-D7, (D8)
CKE0
D0-D7, (D8)
Note: D8 is only used in the x72 ECC version.
DQMB4
DQ(39:32)
DQMB5
DQ(47:40)
CS WE
DQM
DQ0-DQ7
D4
CS WE
DQM
DQ0-DQ7
D5
DQMB6
DQ(55:48)
CS WE
DQM
DQ0-DQ7
D6
DQMB7
DQ(63:56)
CS WE
DQM
DQ0-DQ7
D7
E2PROM (256 word x 8 Bit)
SA0 SA0
SA1 SA1 SDA
SA2 SA2 WP
SCL SCL
47 kΩ
CLK0
CLK1
CLK2
CLK3
Clock Wiring
16 M x 64
16 M x 72
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
SPB03958
Block Diagram for 8M × 64/72 SDRAM DIMM Modules (HYS 64/72V8200GU)
Semiconductor Group
5
1998-08-01
5 Page 
HYS 64(72)V8200/16220GU-8/-10
SDRAM Modules
Notes
1. The specified values are valid when addresses are changed no more than once during tCK(MIN.)
and when No Operation commands are registered on every rising clock edge during tRC(MIN.).
Values are shown per module bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(MIN.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1V/ns edge rate
between 0.8 V and 2.0 V.
.
t CH
CLOCK
2.4 V
0.4 V
t CL t T
t SETUP
t HOLD
INPUT
1.4 V
OUTPUT
tAC
t LZ
tAC
t OH
1.4 V
t HZ
SPT03404
I/O
50 pF
Measurement conditions for
tAC and tOH
5. If clock rising time is longer than 1ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
6. Rated at 1.5 V
7. If tT is longen than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“ the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
Semiconductor Group
11
1998-08-01
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HYS72V8200GU-10.PDF ] | |
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