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EDS2508APSA 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EDS2508APSA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 EDS2508APSA 자료 제공

부품번호 EDS2508APSA 기능
기능 256M bits SDRAM
제조업체 Elpida Memory
로고 Elpida Memory 로고


EDS2508APSA 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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EDS2508APSA 데이터시트, 핀배열, 회로
DATA SHEET
256M bits SDRAM
EDS2508APSA (32M words × 8 bits)
EDS2516APSA (16M words × 16 bits)
Description
The EDS2508AP is a 256M bits SDRAM organized as
8,388,608 words × 8 bits × 4 banks. The EDS2516AP
is a 256M bits SDRAM organized as 4194304 words ×
16 bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 60-ball µBGA.
Features
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, full page
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS2508AP)
: UDQM, LDQM (EDS2516AP)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Pin Configurations
/xxx indicates active low signal.
123456
A
VSS DQ15
(DQ7)*
B
DQ14 VSSQ
(NC)*
C
DQ13 VDDQ
(DQ6)*
D
DQ12 DQ11
(NC)* (DQ5)*
E
DQ10 VSSQ
(NC)*
F
DQ9 VDDQ
(DQ4)*
G
DQ8 NC
(NC)*
H
NC VSS
J
NC UDQM
(DQM)*
K
NC CLK
L
CKE A12
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
DQ0 VDD
VDDQ DQ1
(NC)*
VSSQ DQ2
(DQ1)*
DQ4 DQ3
(DQ2)* (NC)*
VDDQ DQ5
(NC)*
VSSQ DQ6
(DQ3)*
NC DQ7
(NC)*
VDD NC
LDQM /WE
(NC)*
/RAS /CAS
NC /CS
BA1 BA0
A0 A10
A2 A1
A3 VDD
(Top view)
Note: ( )* marked pins are for EDS2508APSA.
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0228E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc.2001-2002




EDS2508APSA pdf, 반도체, 판매, 대치품
EDS2508APSA, EDS2516APSA
Electrical Specifications
All voltages are referenced to VSS (GND).
After power up (refer to the Power-up Sequence).
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
Unit Note
–0.5 to VDD + 0.5 (4.6 (max.))
V
–0.5 to +4.6
V
50 mA
1.0 W
0 to +70
–55 to +125
°C
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 0 to 70°C)
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
3.0
3.6
VSS, VSSQ
0
0
Input high voltage
VIH 2.0
VDD + 0.3
Input low voltage
VIL –0.3
0.8
Notes: 1. The supply voltage with all VDD and VDDQ pins must be on the same level.
2. The supply voltage with all VSS and VSSQ pins must be on the same level.
3. VIH (max.) = VDD + 2.0 V for pulse width 3ns at VDD.
4.VIL (min.) = VSS – 2.0 V for pulse width 3ns at VSS.
Unit
V
V
V
V
Notes
1
2
3
4
Data Sheet E0228E30 (Ver. 3.0)
4

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EDS2508APSA 전자부품, 판매, 대치품
EDS2508APSA, EDS2516APSA
Test Conditions
Input and output timing reference levels: 1.4V
Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V 0.8 V
I/O
tT tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-7A
Frequency (MHz)
133
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
7.5
2
8
6
2
2
2
1
4
Self refresh exit to command input
lSEC
8
Precharge command to high impedance
(CL = 2)
(CL = 3)
Last data out to active command
(Auto precharge same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3)
Column command to column command
Write command to data in latency
DQM to data in
lHZP
lHZP
lAPR
lEP
lEP
lCCD
lWCD
lDID
2
3
1
–1
–2
1
0
0
DQM to data out
CKE to CLK disable
lDOD
lCLE
2
1
Register set to active command
lMRD
2
/CS to command disable
lCDD
0
Power down exit to command input
lPEC
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
-75
7.5
3
9
6
3
2
2
1
5
9
2
3
1
–1
–2
1
0
0
2
1
2
0
1
CL
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
Data Sheet E0228E30 (Ver. 3.0)
7

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부품번호상세설명 및 기능제조사
EDS2508APSA

256M bits SDRAM

Elpida Memory
Elpida Memory

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