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EDS2508APTA-75 데이터시트 PDF




Elpida Memory에서 제조한 전자 부품 EDS2508APTA-75은 전자 산업 및 응용 분야에서
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부품번호 EDS2508APTA-75 기능
기능 256M bits SDRAM
제조업체 Elpida Memory
로고 Elpida Memory 로고


EDS2508APTA-75 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



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EDS2508APTA-75 데이터시트, 핀배열, 회로
DATA SHEET
256M bits SDRAM
EDS2504ACTA, EDS2504APTA (64M words × 4 bits)
EDS2508ACTA, EDS2508APTA (32M words × 8 bits)
EDS2516ACTA, EDS2516APTA (16M words × 16 bits)
Description
Pin Configurations
The EDS2504AC/AP is a 256M bits SDRAM organized
as 16,777,216 words × 4 bits × 4 banks. The EDS2508
AC/AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AC/AP is a
256M bits SDRAM organized as 4194304 words × 16
bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 54-pin plastic TSOP (II).
Features
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length* (BL): 1, 2, 4, 8
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS2504AC/AP, EDS2508AC/AP)
: UDQM, LDQM (EDS2516AC/AP)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Note: EDS2504AP/08AP/16AP is supported full page
function.
/xxx indicates active low signal.
Index
Index
EDS2504AC/08AC/16AC
EDS2504AP/08AP/16AP
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0110E30 (Ver. 3.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001




EDS2508APTA-75 pdf, 반도체, 판매, 대치품
EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit Note
Voltage on any pin relative to VSS
VT
–0.5 to VDD + 0.5 (4.6 (max.))
V
Supply voltage relative to VSS
VDD
–0.5 to +4.6
V
Short circuit output current
IOS 50
mA
Power dissipation
PD 1.0
W
Operating temperature
TA 0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Respect to VSS.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 0 to 70°C)
Parameter
Symbol
min.
max.
Supply voltage
VDD, VDDQ
3.0
3.6
VSS, VSSQ
0
0
Input high voltage
VIH 2.0
VDD + 0.3
Input low voltage
VIL –0.3
0.8
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VDD and VDDQ pins must be on the same level.
3. The supply voltage with all VSS and VSSQ pins must be on the same level.
4. VIH (max.) = VDD + 2.0 V for pulse width 3ns at VDD.
5. VIL (min.) = VSS – 2.0 V for pulse width 3ns at VSS.
Unit
V
V
V
V
Notes
1, 2
3
1, 4
1, 5
Data Sheet E0110E30 (Ver. 3.0)
4

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EDS2508APTA-75 전자부품, 판매, 대치품
EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Test Conditions
Input and output timing reference levels: 1.4V
Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V 0.8 V
I/O
tT tT
Output load
Relationship Between Frequency and Minimum Latency
Parameter
-7A
Frequency (MHz)
133
tCK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Symbol
lRCD
lRC
lRAS
lRP
lDPL
lRRD
lSREX
lDAL
7.5
2
8
6
2
2
2
1
4
Self refresh exit to command input
lSEC
8
Precharge command to high impedance
(CL = 2)
(CL = 3)
lHZP
lHZP
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CL = 2)
(CL = 3)
lAPR
lEP
lEP
Column command to column command
lCCD
2
3
1
–1
–2
1
Write command to data in latency
lWCD
0
DQM to data in
DQM to data out
lDID
lDOD
0
2
CKE to CLK disable
Register set to active command
lCLE
lMRD
1
2
/CS to command disable
lCDD
0
Power down exit to command input
lPEC
1
Notes: 1.IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
4. EDS2504AC/08AC/16AC is possible lMRD 1 clock.
-75
7.5
3
9
6
3
2
2
1
5
9
2
3
1
–1
–2
1
0
0
2
1
2
0
1
CL
Notes
1
1
1
1
1
1
2
= [lDPL + lRP]
= [lRC]
3
4
Data Sheet E0110E30 (Ver. 3.0)
7

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