EDS5116ABTA Datasheet PDF - Elpida Memory
| Part Number | EDS5116ABTA | |
| Description | 512M bits SDRAM | |
| Manufacturers | Elpida Memory | |
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PRELIMINARY DATA SHEET
512M bits SDRAM
EDS5104ABTA (128M words × 4 bits)
EDS5108ABTA (64M words × 8 bits)
EDS5116ABTA (32M words × 16 bits)
Description
Pin Configurations
The EDS5104AB is a 512M bits SDRAM organized as
33,554,432 words × 4 bits × 4 banks. The EDS5108AB
is a 512M bits SDRAM organized as 16,777,216 words
× 8 bits × 4 banks. The EDS5116AB is a 512M bits
SDRAM organized as 8,388,608 words × 16 bits × 4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54-
pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 166MHz/133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS5104AB, EDS5108AB)
: UDQM, LDQM (EDS5116AB)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
/xxx indicates active low signal.
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0250E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
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EDS5104ABTA, EDS5108ABTA, EDS5116ABTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
max.
/CAS latency
Symbol Grade × 4 × 8 × 16 Unit Test condition
Notes
Operating current
ICC1
-6B,-7A 160 165 175
-75 140 145 155
mA
Burst length = 1
tRC = tRC (min.)
1, 2, 3
Standby current in power
down
ICC2P
333
mA
CKE = VIL,
tCK = tCK (min.)
6
Standby current in power
down (input signal stable)
ICC2PS
222
mA CKE = VIL, tCK = ∞ 7
Standby current in non
power down
ICC2N
-6B 30
-7A, -75 25
30
25
30
25
mA
CKE, /CS = VIH,
tCK = tCK (min.)
4
Standby current in non
power down (input signal ICC2NS
stable)
999
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
Active standby current in
power down
ICC3P
444
mA
CKE = VIL,
tCK = tCK (min.)
1, 2, 6
Active standby current in
power down (input signal ICC3PS
stable)
333
mA CKE = VIL, tCK = ∞ 2, 7
Active standby current in
non power down
ICC3N
-6B 45
-7A, -75 40
45
40
45
40
mA
CKE, /CS = VIH,
tCK = tCK (min.)
1, 2, 4
Active standby current in
non power down (input
signal stable)
ICC3NS
20 20 20
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
Burst operating current ICC4
-6B 160 170 190
-7A, -75 130 140 160
mA tCK = tCK (min.), BL = 4 1, 2, 5
Refresh current
Self refresh current
ICC5
ICC6
-6B,-7A 320 320 320
-75 280 280 280
444
mA tRC = tRC (min.)
3
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
ILI
ILO
VOH
VOL
min.
–1
–1.5
2.4
—
max.
1
1.5
—
0.4
Unit Test condition
Notes
µA 0 ≤ VIN ≤ VDD
µA 0 ≤ VOUT ≤ VDD, DQ = disable
V IOH = –4 mA
V IOL = 4 mA
Preliminary Data Sheet E0250E10 (Ver. 1.0)
5
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