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EL2005 데이터시트 PDF




Elantec에서 제조한 전자 부품 EL2005은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 EL2005 기능
기능 High Accuracy Fast Buffer
제조업체 Elantec
로고 Elantec 로고


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EL2005 데이터시트, 핀배열, 회로
EL2005 EL2005C
High Accuracy Fast Buffer
Features
 Low input current 50 pA
 Low offset and drift
2 mV 25 mV C
 High slew rate 1500 V ms
 Fast rise and fall time 2 5 ns
 High input resistance 1000 GX
 Bandwidth 140 MHz
 Pin compatible with ELH0033
 MIL-STD-883 Revision C devices
manufactured in U S A
Advantages
 No input loading
 Input current independent of
input voltage
 Eliminates offset adjustments
 Drives cables directly
Ordering Information
Part No
Temp Range Package Outline
EL2005CG b25 C to a85 C TO-8 MDP0002
EL2005G
b55 C to a125 C TO-8 MDP0002
EL2005G 883B b55 C to a125 C TO-8 MDP0002
General Description
The EL2005 is a high-speed FET input buffer similar to
ELH0033 and EL2004 but with input specifications significant-
ly improved over the previous types The input stage employs a
cascode configuration to maintain constant input characteris-
tics over the full g10V input range The input looks like a 3 pF
capacitor to ground in almost all cases since the DC bias current
is constant with input voltage In sample and hold circuits this
results in an order of magnitude improvement in hold charac-
teristics Input offset voltage and offset voltage drift are also
improved a factor of two over previous types
These excellent DC characteristics are complemented by a wide
140 MHz bandwidth while the 1500 V ms slew rate and excel-
lent phase linearity of the ELH0033 family are preserved allow-
ing direct plug-in replacement for upgraded performance (For
even faster operation see EL2004 )
Elantec facilities comply with MIL-I-45208A and are MIL-
STD-1772 certified Elantec’s Military devices comply with
MIL-STD-883B Revision C and are manufactured in our rigidly
controlled ultra-clean facilities in Milpitas California For ad-
ditional information on Elantec’s Quality and Reliability Assur-
ance Policy and procedures request brochure QRA-1
Simplified Schematic
Connection Diagram
Top View
Note Case is electrically isolated
2005 – 1
2005 – 2
Note All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication however this data sheet cannot be a ‘‘controlled document’’ Current revisions if any to these
specifications are maintained at the factory and are available upon your request We recommend checking the revision level before finalization of your design documentation Patent pending
CMS 2005DS
1989 Elantec Inc




EL2005 pdf, 반도체, 판매, 대치품
EL2005 EL2005C
High Accuracy Fast Buffer
Typical Performance Curves
Maximum Power
Dissipation
Gain vs Input Voltage
Output Resistance vs
Output Current
Frequency Response
Supply Current vs
Supply Voltage
Offset Voltage vs
Supply Voltage
Input Bias Current vs
Input Voltage
Input Bias Current vs
Temperature
Input Bias Current
During Warm-up
2005 – 3
Rise Time vs
Temperature
Small Signal Pulse
Response
Large Signal Pulse
Response
2005 – 4
4

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EL2005 전자부품, 판매, 대치품
EL2005 EL2005C
High Accuracy Fast Buffer
Applications Information
Recommended Layout Precautions
RF video printed circuit board layout rules
should be followed when using the EL2005 since
it will provide power gain to frequencies over
100 MHz Ground planes are recommended and
power supplies should be decoupled at each de-
vice with low inductance capacitors In addition
ground plane shielding may be extended to the
metal case of the device since it is electrically iso-
lated from internal circuitry Alternatively the
case should be connected to the output to mini-
mize input capacitance
Offset Voltage Adjustment
The EL2005’s offset voltages have been actively
trimmed by laser to meet guaranteed specifica-
tions when the offset preset pin is shorted to the
offset adjust pin The pre-calibration allows the
devices to be used in most DC or AC applications
without individually offset nulling each device If
offset null is desirable it is simply obtained by
leaving the offset preset pin open and connecting
a trim pot of 200X between the offset adjust pin
and Vb as illustrated on page 4
Operation from Single or Asymmetrical
Power Supplies
This device type may be readily used in applica-
tions where symmetrical supplies are unavailable
or not desirable In this case an apparent output
offset occurs due to the device’s voltage gain of
less than unity This additional output offset er-
ror may be predicted by
(Va bVb)
DVOj(1bAV) 2 e0 005 (Va bVb)
where AV e No load voltage gain typically 0 99
Vae Positive supply voltage
Vbe Negative supply voltage
For example with Va e a5V and Vb e
b12V DVO would be b35 mV This may be ad-
justed to zero as described above
Short Circuit Protection
In order to optimize transient response and out-
put swing output current limit has been omitted
from the EL2005 Short circuit protection may be
added by inserting appropriate value resistors be-
tween Va and VCa pins and Vb and VCb pins
as shown on page 4
Resistor values may be predicted by
Va Vb
RLIM j ISC e ISC
where ISC s 100 mA for EL2005
The inclusion of limiting resistors in the collec-
tors of the output transistors reduces output volt-
age swing Decoupling VCa and VCb pins with
capacitors to ground will retain full output swing
for transient pulses An alternate active current
limit technique that retains full DC output swing
is also shown on page 4 In this circuit the cur-
rent sources are saturated during normal opera-
tion thus applying full supply voltage to the VC
pins Under fault conditions the voltage decreas-
es as required by the overload
RLIM
j
VBE
ISC
e
0
60
6V
mA
e
10X
Capacitive Loading
The EL2005 is designed to drive capacitive loads
such as coaxial cables in excess of several thou-
sand picofarads without susceptibility to oscilla-
tion However peak current resulting from
(C c dV dt) should be limited below absolute
maximum peak current ratings for the devices
Thus
DVIN
Dt
c
CL
s
IOUT
s
g250
mA
In addition power dissipation resulting from
driving capacitive loads plus standby power
should be kept below the total package power
rating
PDpkg t PDC a PAC
PDpkg t (Va b Vb) c IS a PAC
PAC j (VP-P)2 c f c CL
where VP-P e Peak-to-peak output voltage
swing
f e Frequency
CL e Load Capacitance
7

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