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M48Z512AY 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 M48Z512AY은 전자 산업 및 응용 분야에서
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부품번호 M48Z512AY 기능
기능 4 Mbit (512 Kbit x 8) ZEROPOWER SRAM
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M48Z512AY 데이터시트, 핀배열, 회로
M48Z512A
M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER® SRAM
Not recommended for new design
Features
Integrated, ultra low power SRAM, power-fail
control circuit, and battery
Conventional SRAM operation; unlimited
)WRITE cycles
t(s10 years of data retention in the absence of
cpower
duAutomatic power-fail chip deselect and WRITE
roprotection
PTwo WRITE protect voltages:
te(VPFD = power-fail deselect voltage)
le– M48Z512A: VCC = 4.75 to 5.5 V;
4.5 V VPFD 4.75 V
so– M48Z512AY: VCC = 4.5 to 5.5 V;
b4.2 V VPFD 4.5 V
O– M48Z512AV: VCC = 3.0 to 3.6 V;
-2.8 V VPFD 3.0 V
t(s)Battery internally isolated until power is applied
cPin and function compatible with JEDEC
ustandard 512 K x 8 SRAMs
rodPMDIP32 is an ECOPACK® package
RoHS compliant
Obsolete P– Lead-free second level interconnect
32
1
PMDIP32 module
Description
The M48Z512A/Y/V ZEROPOWER® RAM is a
non-volatile, 4,194,304-bit static RAM organized
as 524,288 words by 8 bits. The devices combine
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module.
June 2011
Doc ID 5146 Rev 9
This is information on a product still in production but not recommended for new designs.
1/21
www.st.com
1




M48Z512AY pdf, 반도체, 판매, 대치품
List of figures
List of figures
M48Z512A, M48Z512AY, M48Z512AV
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8
Figure 5. Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9.
Figure 10.
)Figure 11.
Obsolete Product(s) - Obsolete Product(sFigure 12.
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PMDIP32 – 32-pin plastic DIP module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4/21 Doc ID 5146 Rev 9

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M48Z512AY 전자부품, 판매, 대치품
M48Z512A, M48Z512AY, M48Z512AV
2 Operating modes
Operating modes
The M48Z512A/Y/V also has its own power-fail detect circuit. The control circuitry constantly
monitors the single VCC supply for an out of tolerance condition. When VCC is out of
tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low VCC. As VCC falls below the
switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
The ZEROPOWER® RAM replaces industry standard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special WRITE timing or limitations on the number of
) - Obsolete Product(s)Note:
Obsolete Product(s2.1
WRITEs that can be performed.
Table 2. Operating modes
Mode
VCC
EG
Deselect
4.75 to 5.5 V
VIH X
WRITE
READ
or
4.5 to 5.5 V
or
VIL X
VIL VIL
READ
3.0 to 3.6 V
VIL VIH
Deselect
VSO to VPFD (min)(1)
X
X
Deselect
VSO(1)
XX
1. X = VIH or VIL; VSO = battery backup switchover voltage.
W
X
VIL
VIH
VIH
X
X
DQ0-DQ7
Power
High Z
DIN
DOUT
High Z
High Z
High Z
Standby
Active
Active
Active
CMOS standby
Battery backup mode
See Table 10 on page 16 for details.
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The device architecture allows ripple-through access of data from eight of
4,194,304 locations in the static storage array. Thus, the unique address specified by the 19
address inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data
will be available at the data I/O pins within address access time (tAVQV) after the last
address input signal is stable, providing that the E (chip enable) and G (output enable)
access times are also satisfied. If the E and G access times are not met, valid data will be
available after the later of chip enable access time (tELQV) or output enable access Time
(tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the
outputs are activated before tAVQV, the data lines will be driven to an indeterminate state
until tAVQV. If the address inputs are changed while E and G remain low, output data will
remain valid for output data hold time (tAXQX) but will go indeterminate until the next address
access.
Doc ID 5146 Rev 9
7/21

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관련 데이터시트

부품번호상세설명 및 기능제조사
M48Z512A

4 Mbit (512 Kbit x 8) ZEROPOWER SRAM

ST Microelectronics
ST Microelectronics
M48Z512AV

4 Mbit (512 Kbit x 8) ZEROPOWER SRAM

STMicroelectronics
STMicroelectronics

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