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부품번호 | PD45128441G5-A75A-9JF 기능 |
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기능 | 128M-bit Synchronous DRAM 4-bank/ LVTTL | ||
제조업체 | Elpida Memory | ||
로고 | |||
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control (×16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0031N30 (Ver. 3.0)
Date Published August 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µPD45128441, 45128841, 45128163
Pin Configurations
/xxx indicates active low signal.
[µPD45128441]
54-pin Plastic TSOP (II) (10.16mm (400))
8M words × 4 bits × 4 banks
VCC
NC
VCCQ
NC
DQ0
VSSQ
NC
NC
VCCQ
NC
DQ1
VSSQ
NC
VCC
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Vss
53 NC
52 VssQ
51 NC
50 DQ3
49 VccQ
48 NC
47 NC
46 VssQ
45 NC
44 DQ2
43 VccQ
42 NC
41 Vss
40 NC
39 DQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
A0 to A11 Note
: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ3
: Data inputs / outputs
CLK : Clock input
CKE
: Clock enable
/CS : Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE : Write enable
DQM
: DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ
: Supply voltage for DQ
VSSQ
: Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A9, A11 : Column address inputs
4 Data Sheet E0031N30
4페이지 Block Diagram
CLK
CKE
Clock
Generator
Address
Mode
Register
/CS
/RAS
/CAS
/WE
µPD45128441, 45128841, 45128163
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Data Sheet E0031N30
7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ PD45128441G5-A75A-9JF.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
PD45128441G5-A75A-9JF | 128M-bit Synchronous DRAM 4-bank/ LVTTL | Elpida Memory |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |