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PD488588FF-C60-53-DH1 데이터시트 PDF




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부품번호 PD488588FF-C60-53-DH1 기능
기능 288M bits Direct Rambus DRAM
제조업체 Elpida Memory
로고 Elpida Memory 로고


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PD488588FF-C60-53-DH1 데이터시트, 핀배열, 회로
DATA SHEET
288M bits Direct Rambus DRAM
for High Performance Solution
µPD488588FF-C80-40 (512K words × 18 bits × 32s banks)
Description
The Direct Rambus DRAM (Direct RDRAM) is a
general purpose high-performance memory device
suitable for use in a broad range of applications
including computer memory, graphics, video, and any
other application where high bandwidth and low
latency are required.
The µPD488588FF is 288Mbits Direct Rambus DRAM
(RDRAM), organized as 16M words by 18 bits.
The use of Rambus Signaling Level (RSL) technology
permits 800MHz transfer rates while using
conventional system and board design technologies.
Direct RDRAM devices are capable of sustained data
transfers at 1.25ns per two bytes (10ns per sixteen
bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simultaneous
randomly addressed memory transactions.
The separate control and data buses with independent
row and column control yield over 95% bus efficiency.
The Direct RDRAM’s four banks support up to four
simultaneous transactions.
System oriented features for mobile, graphics and
large memory systems include power management,
byte masking.
The µPD488588FF is offered in a CSP horizontal
package suitable for desktop as well as low-profile
add-in card and mobile applications. Direct RDRAMs
operate from a 2.5V supply.
Features
Highest sustained bandwidth per DRAM device
— 1.6 GB/s sustained data transfer rate
— Separate control and data buses for maximized
efficiency
— Separate row and column control buses for easy
scheduling and highest performance
— 32 banks: four transactions can take place
simultaneously at full bandwidth data rates
Low latency features
— Write buffer to reduce read latency
— 3 precharge mechanisms for controller flexibility
— Interleaved transactions
Advanced power management:
— Multiple low power states allows flexibility in power
consumption versus time to active state
— Power-down self-refresh
Overdrive current mode
Organization: 2K bytes pages and 32 banks, x 18
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
Package : 80-ball FBGA (µ BGA) (17.16 × 10.2)
Application
The µPD488588FF is most appropriate for the
applications, such as consumer products demanding
vivid animations, processor memory for multimedia
and 3D graphics, network processing and storage
systems requiring scalability to accommodate future
designs.
Document No. E0251N20 (Ver. 2.0)
Date Published July 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.




PD488588FF-C60-53-DH1 pdf, 반도체, 판매, 대치품
µPD488588FF-C80-40
Pin Description
Signal
Input / Output Type #pins
Description
SIO0, SIO1
CMD
SCK
Input / Output CMOS Note1 2
Input
CMOS Note1
1
Input
CMOS Note1
1
Serial input/output. Pins for reading from and writing to the control registers using
a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from
and writing to the control registers. Also used for power management.
Serial clock input. Clock source used for reading from and writing to the control
registers.
VDD 18 Supply voltage for the RDRAM core and interface logic.
VDDa 1 Supply voltage for the RDRAM analog circuitry.
VCMOS
2 Supply voltage for CMOS input/output pins.
GND
22 Ground reference for RDRAM core and interface.
GNDa
2 Ground reference for RDRAM analog circuitry.
DQA8..DQA0 Input / Output RSL Note2
CFM
Input
RSL Note2
CFMN
Input
RSL Note2
9 Data byte A. Nine pins which carry a byte of read or write data between the
Channel and the RDRAM.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
VREF
CTMN
Input
RSL Note2
CTM
Input
RSL Note2
ROW2..ROW0
Input
RSL Note2
COL4..COL0
Input
RSL Note2
DQB8..DQB0 Input / Output RSL Note2
1 Logic threshold reference voltage for RSL signals.
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
3 Row access control. Three pins containing control and address information for
row accesses.
5 Column access control. Five pins containing control and address information for
column accesses.
9 Data byte B. Nine pins which carry a byte of read or write data between the
Channel and the RDRAM.
Total pin count per package
80
Notes 1.All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.
2.All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
4 Data Sheet E0251N20 (Ver. 2.0)

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PD488588FF-C60-53-DH1 전자부품, 판매, 대치품
µPD488588FF-C80-40
38. IDD - Supply Current Profile .................................................................................................................................67
39. Capacitance and Inductance ..............................................................................................................................68
40. Interleaved Device Mode .....................................................................................................................................70
41. Glossary of Terms ...............................................................................................................................................74
42. Package Drawing .................................................................................................................................................76
43. Recommended Soldering Conditions ................................................................................................................77
Data Sheet E0251N20 (Ver. 2.0)
7

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부품번호상세설명 및 기능제조사
PD488588FF-C60-53-DH1

288M bits Direct Rambus DRAM

Elpida Memory
Elpida Memory

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