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부품번호 PDI1394L40BE 기능
기능 1394 enhanced AV link layer controller
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PDI1394L40BE 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
SEE THE LAST 2 PAGES OF THIS DATASHEET FOR A LIST OF ERRATA RELATED TO THIS PART.
PDI1394L40
1394 enhanced AV link layer controller
Preliminary specification
Supersedes data of 2000 May 15
2000 Dec 15
Philips
Semiconductors




PDI1394L40BE pdf, 반도체, 판매, 대치품
Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
1.0 FEATURES
IEEE1394a and IEEE1394–1995 Standard Link Layer Controller
Hardware Support for the IEC61883 International Standard of
Digital Interface for Consumer Electronics
Interface to any IEEE 1394–1995 or 1394a Physical Layer
Interface
5 V Tolerant I/Os
Single 3.3 V supply voltage
Full-duplex isochronous operation
Operates with 400/200/100 Mbps physical layer devices
12K byte fully programmable FIFO pool for isochronous and
asynchronous data
Supports single capacitor isolation mode and IEEE 1394–1995,
Annex J. isolation
6-field deep SYT buffer added to enhance real-time isochronous
synchronization using the AVFSYNC pin
Generates its own AV port clocks under software control. Select
one of three frequencies: 24.576, 12.288, or 6.144 MHz
On chip timer resources
Flexible 8/16 bit multiplexed/non-multiplexed host interface
Parallel AV interface
2.0 DESCRIPTION
The PDI11394L40, Philips Semiconductors Full Duplex 1394
Audio/Video (AV) Link Layer Controller, is an IEEE 1394a–2000
compliant link layer controller featuring 2 embedded AV layer
interfaces.
The application data is packetized according to the IEC 61883
International Standard of Interface for Consumer Electronic
Audio/Video Equipment. Both AV layer interfaces are byte-wide
ports capable of accommodating various MPEG–2 and DVC
codecs. A flexible host interface is provided for internal register
configuration as well as performing asynchronous data transfers.
Both 8 bit and 16 bit wide data paths, as well as
multiplexed/non-multiplexed access modes are supported.
The PDI1394L40 is powered by a single 3.3 V power supply and the
inputs and outputs are 5 V tolerant. It is available in the LQFP144
package.
3.0 QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C
SYMBOL
PARAMETER
VDD
IDD
SCLK
Functional supply voltage range
Supply current @ VDD = 3.3 V
Device clock
CONDITIONS
Operating
MIN
3.0
49.147
TYP
3.3
110
49.152
MAX
3.6
200
49.157
UNIT
V
mA
MHz
4.0 ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
144-pin LQFP144
0 to +70 °C
OUTSIDE NORTH AMERICA
PDI1394L40BE
NORTH AMERICA
PDI1394L40BE
PKG. DWG. #
SOT486–1
NOTE:
This datasheet is subject to change.
Please visit our internet website www.semiconductors.philips.com/1394 for latest changes.
2000 Dec 15
1

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PDI1394L40BE 전자부품, 판매, 대치품
Philips Semiconductors
1394 enhanced AV link layer controller
Preliminary specification
PDI1394L40
8.0 APPLICATION DIAGRAM
MPEG OR DVC
DECODER
AV
INTERFACE
MPEG OR DVC
DECODER
AV
INTERFACE
PDI1394L40
AV LINK
DATA 16/
ADDRESS 9/
INTERRUPT & CONTROL
PHY–LINK
INTERFACE
PDI1394Pxx
PHY
1394 CABLE
INTERFACE
HOST CONTROLLER
SV01835
9.0 PIN DESCRIPTION
9.1 Host Interface
PIN No.
PIN SYMBOL I/O NAME AND FUNCTION
13, 14, 15, 16, 19,
20, 21, 22
HIF AD[7:0]
I/O Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers.
1, 2, 3, 4, 7, 8, 9,
10
HIF D[15:8]
I/O
Host Interface Data 15 (MSB) through 8. Only used in 16 bit access mode (HIF
16BIT = HIGH).
26, 27, 28, 29, 30,
31, 32, 33
HIF A[7:0]
I/O
Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal
registers. See description of Host Interface for addressing rules (Section 12.5).
Control bit used to indicate the first byte/word of a read function or the last byte/word of a write
25
HIF A8
I function so that the data quadlet is fetched or stored. See Section 12.5 for more information
regarding the host interface.
36
HIF CSN
I
Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control
and status registers.
Write enable. When asserted (LOW) in conjunction with HIF CSN, a write to the PDI1394L40
internal registers is requested. (NOTE: HIF WRN and HIF RDN : if these are both LOW in
37
HIF WRN
I conjunction with HIF CSN, then a write cycle takes place. This can be used to connect CPUs
that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the
R/W_N line to the HIF WRN and tie HIF RDN LOW.)
Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L40. Read the General
38
HIF INTN
O Interrupt Register for more information. This pin is open drain and requires a 1KW pull-up
resistor.
39
HIF ALE
I Address latch enable. Used in multiplex mode only.
40
HIF RDN
I
Read enable. When asserted (LOW) in conjunction with HIF CSN, a read of the PDI1394L40
internal registers is requested.
41
HIF WAIT
O Wait signal. Signals Host interface in WAIT condition when HI. See Section 12.5.
42
RESETN
I Reset (active LOW). The asynchronous master reset to the PDI1394L40.
45
HIF 16BIT
I
Host interface mode pin. When LOW HIF operates in 8 bit mode. When HIGH HIF operates in
16 bit mode.
Host interface mode pin. When LOW HIF operates in non-multiplex mode, when HIGH HIF
46
HIF MUX
I operates in multiplex mode. When HIGH, the low-order eight address bits are multiplexed with
data on HIF AD[7:0], otherwise they are non-multiplexed and supplied on A[7:0].
2000 Dec 15
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PDI1394L40BE

1394 enhanced AV link layer controller

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