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부품번호 PDI1394P11ABD 기능
기능 3-port physical layer interface
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PDI1394P11ABD 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PDI1394P11A
3-port physical layer interface
Preliminary specification
1999 Mar 10
Philips
Semiconductors




PDI1394P11ABD pdf, 반도체, 판매, 대치품
Philips Semiconductors
3-port physical layer interface
Preliminary specification
PDI1394P11A
6.0 BLOCK DIAGRAM
CPS
LPS
ISO–
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
PC0
PC1
PC2
C/LKON
TESTM1
TESTM2
LINK
INTERFACE
RECEIVED
DATA
DECODER/
TIMER
ARBITRATION
AND CONTROL
STATE
MACHINE
LOGIC
BIAS
VOLTAGE AND
CURRENT
GENERATOR
PORT 1
R0
R1
TPBIAS1
TPBIAS2
TPBIAS3
TPA1+
TPA1–
TPB1+
TPB1–
PORT 2
PORT 3
TPA2+
TPA2–
TPB2+
TPB2–
TPA3+
TPA3–
TPB3+
TPB3–
RESET–
PD
TRANSMIT
DATA
ENCODER
CRYSTAL
OSCILLATOR
PLL SYSTEM
& TRANSMIT
CLOCK
GENERATOR
XI
XO
FILTER
SV00228
7.0 FUNCTIONAL SPECIFICATION
The PDI1394P11A is an IEEE1394–1995 High Performance Serial
Bus Specification compliant physical layer interface device. It
provides an interface between an attached link layer controller and
three 1394 cable interface ports. In addition to the interface function,
the PDI1394P11A performs bus initialization and arbitration
functions as well as monitoring line conditions and connection
status.
7.1 Clocking
The PDI1394P11A utilizes a stable internal reference clock of
196.608 MHz. The reference clock is generated using an external
24.576 MHz crystal and an internal Phase Locked Loop (PLL). The
PLL clock is divided down to 49.152 MHz and 98.304 MHz clock
signals. The 49.152 MHz clock is used for internal logic and
provided as an output to clock a link layer controller. The 196.608
MHz and 98.304 MHz clocks are used for synchronization of the
transmitted strobe and data information.
7.2 Port Interfaces
The PDI1394P11A provides the transceiver functions needed to
implement a three port node in a cable-based 1394 network. Each
cable port incorporates two differential line transceivers. In addition
to transmission and reception of packet data, the line transceivers
monitor conditions on the cable to determine connection status, data
speed, and bus arbitration states.
The PDI1394P11A receives data to be transmitted over the bus from
two or four parallel data paths to the Link Controller, D[0:3]. These
data paths are latched and synchronized with the 49.152 MHz clock.
The parallel bit paths are combined serially, encoded and
transmitted at either 98.304 Mb/s or 196.608 Mb/s, depending
whether the transaction is a 100 Mb/s or 200 Mb/s transfer,
respectively. The transmitted data is encoded as data-strobe
information, with the data information being transmitted on the TPB
cable pairs and the strobe information transmitted on the TPA cable
pairs.
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair and the strobe information is received on the TPB cable pair.
The combination of the data and strobe signals is decoded to
recover the receive clock signal and the serial data stream. The
serial data stream is converted to two or four parallel bit streams,
resynchronized to the internal 49.152 MHz clock and sent to the
1999 Mar 10
4

4페이지










PDI1394P11ABD 전자부품, 판매, 대치품
Philips Semiconductors
3-port physical layer interface
Preliminary specification
PDI1394P11A
12.0 OTHER DEVICE I/O
SYMBOL
PARAMETER
IDD Supply current
VP Cable Power Threshold Voltage
VOH High-level output voltage
VOL Low-level output voltage
II
Input current, LREQ, LPS, PD,
TESTM[1:2]
IOZ
OFF-state output current, CTLn,
Dn, C/LKON I/Os, PC[0:2] inputs
IPU Pullup current, RESET– input
IPD Pulldown current, RESET– input
VTH+
VTH–
VTH–SP
VIT+
VIT–
VO
Ib
Power-up reset time, RESET– input
Positive arbitration comparator threshold
voltage
Negative arbitration comparator threshold
voltage
Speed signal input threshold voltage
Positive going input threshold voltage,
LREQ, CTLn, Dn inputs
Negative going input threshold voltage,
LREQ, CTLn, Dn inputs
TPBIASn output voltage
Absolute value of bus holding current
LREQ, PD, CTLn, Dn inputs, LPS
TEST CONDITION
One port transmitting
VDD = 3.3 V One port receiving
One port not connected
VDD = 3.6 V
VDD = 3.6 V Power-down mode
RL = 400 kto CPS pin
IOH = Max., VDD = Min.
IOL = Min., VDD = Max.
VI = 5.5 V or 0 V, ISO– = 0
VO = 5.5 V or 0 V, ISO– = 0
VI = 1.5 V
VI = 0 V
VI = VDD
PD = high
C = 0.1 µf
ISO– = high, VI = 0.5 VDD
LIMITS
MIN TYP MAX
60
1.5
4.7
VDD – 0.55
2
–20 –40
–22 –45
100 260
2
89
175
5
7.5
0.5
±1.0
±5.0
–80
–90
450
168
–168
49
VDD/2 + 0.12
–89
131
VDD/2 + 0.66
VDD/2 – 0.66
VDD/2 – 0.12
1.665 1.85 2.015
190
UNIT
mA
mA
mA
V
V
V
µA
µA
µA
µA
µA
ms
mV
mV
mV
V
V
V
µA
13.0 THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
RΘjA
RΘjC
Junction-to-free-air thermal resistance
Junction-to-case thermal resistance
Board mounted, no air flow
LIMITS
UNIT
MIN TYP MAX
92.5 °C/W
10.4 °C/W
1999 Mar 10
7

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PDI1394P11ABD

3-port physical layer interface

NXP Semiconductors
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