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기능 3-port physical layer interface
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PDI1394P22BD 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PDI1394P22
3-port physical layer interface
Objective specification
1999 Jul 09
Philips
Semiconductors




PDI1394P22BD pdf, 반도체, 판매, 대치품
Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P22
Name
C/LKON
Pin Type
CMOS 5V tol
Pin Numbers
18
DGND
D0–D7
DVDD
Supply
2, 14, 25, 56, 64
CMOS 5V tol
Supply
5, 6, 8, 9, 10, 11,
12, 13
7, 17, 26, 27, 62
/ISO
CMOS
23
LPS CMOS 5V tol 16
LREQ
CMOS 5V tol 1
PC0, PC1, CMOS 5V tol 20, 21, 22
PC2
PD CMOS 5V tol 19
PLLGND
PLLVDD
Supply
Supply
58
57
/RESET
CMOS 5V tol 61
1999 Jul 09
I/O Description
I/O Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10kresistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is deasserted low when
the LPS input terminal is active.
— Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
I/O Data I/Os. These are bi-directional data signals between the
PDI1394P22 and the LLC. Bus holders are built into these terminals.
— Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
I Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P22 and LLC, the /ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the /ISO terminal should be tied high to disable the
differentiation logic.
I Link Power Status input. This terminal is used to monitor the power
status of the LLC, and is connected to either the VDD supplying the link
layer controller through a 1kresistor, or to a pulsed output which is
active when the LLC is powered. The pulsed output is useful when using
an isolation barrier. If this input is low for more than 25 ms, the LLC is
considered powered down. If this input is high for more than 20 ns, the
LLC is considered powered up. If the LLC is powered-down, the
PHY–LLC interface is disabled, and the PDI1394P22 performs only the
basic repeater functions required for network initialization and operation.
Bus holder is built into this terminal.
I LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P22. Bus holder is built into this terminal.
I Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 18 for encoding.
I Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. Bus holder is built into this terminal. For more information, refer to
Section 17.3
— PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
— PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. Lower frequency 10 µF filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
I Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to VDD is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
4

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PDI1394P22BD 전자부품, 판매, 대치품
Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P22
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signalling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PDI1394P22 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. the PHY contains three
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.
The line drivers in the PDI1394P22 operate in a high-impedance
current mode, and are designed to work with external 112
line-termination resistor networks in order to match the 110 cable
impedance. One network is provided at each end of all twisted-pair
cable. Each network is composed of a pair of series-connected 56
resistors. The midpoint of the pair of resistors that is directly
connected to the twisted-pair A terminals is connected to its
corresponding TPBIAS voltage terminal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kand 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor has a value of 6.34 k±1%.
When the power supply of the PDI1394P22 is removed while the
twisted-pair cables are connected, the PDI1394P22 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
When the PDI1394P22 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then
pulled to ground, or the TPB+ and TPB– terminals can be connected
to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.
The TEST0 and TEST1 terminals are used to set up various
manufacturing test conditions. For normal operation, the TEST0 and
TEST1 terminals should be connected to ground.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 18 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all three ports of the PDI1394P22 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the /RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high output when all
twisted-pair cable ports are disconnected, and can be used along
with LPS to determine when to power down the PDI1394P22. The
CNA output is not debounced. In Power Down mode, the CNA
detection circuitry remains enabled.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC indicates to the PHY that the LLC is powered up and
active. During LLC Power Down mode, as indicated by the LPS
input being low for more than 25 µs, the PDI1394P22 deactivates
the PHY-LLC interface to save power. The PDI1394P22 continues
the necessary repeater function required for network operation
during this low power state.
If the PHY receives a link-on packet from another node, the C/LKON
terminal is activated to output a square-wave signal. The LLC
recognizes this signal, reactivates any powered-down portions of the
LLC, and notifies the PHY of its power-on status via the LPS
terminal. The PHY confirms notification by deactivating the
square-wave signal on the C/LKON terminal, then enables the
PHY-link interface.
1999 Jul 09
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PDI1394P22BD

3-port physical layer interface

NXP Semiconductors
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