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PDI1394P25EC 데이터시트 PDF




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부품번호 PDI1394P25EC 기능
기능 1-port 400 Mbps physical layer interface
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PDI1394P25EC 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PDI1394P25
1-port 400 Mbps physical layer interface
Preliminary data
Supersedes data of 2001 Jul 18
2001 Sep 06
Philips
Semiconductors




PDI1394P25EC pdf, 반도체, 판매, 대치품
Philips Semiconductors
1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P25
4.2 LFBGA CONFIGURATION
BOTTOM (BALL) VIEW
1
2
3
4
5
6
7
8
A BCD E F GH
Ball Signal
A1 AGND
A2 NC
A3 NC
A4 R1
A5 AGND
A6 TPBIAS0
A7 TPB0–
A8 AGND
B1 AGND
B2 AGND
B3 NC
B4 NC
B5 TPA0+
B6 TPA0–
B7 AGND
B8 AVDD
Ball Signal
C1 RESET
C2 AVDD
C3 AVDD
C4 NC
C5 AVDD
C6 TPB0+
C7 AVDD
C8 TEST0
D1 PLLVDD
D2 AVDD
D3 PLLGND
D4 PLLVDD
D5 R0
D6 BRIDGE
D7 TESTM
D8 DVDD
Ball Signal
E1 PLLGND
E2 XI
E3 XO
E4 D2
E5 CPS
E6 DVDD
E7 PC1
E8 ISO
F1 DVDD
F2 DVDD
F3 CNA
F4 D4
F5 D6
F6 C/LKON
F7 PC0
F8 PC2
SV01909
Ball Signal
G1 DGND
G2 DGND
G3 CTL0
G4 CTL1
G5 D5
G6 PD
G7 DGND
G8 DGND
H1 LREQ
H2 SYSCLK
H3 D0
H4 D1
H5 D3
H6 D7
H7 LPS
H8 DGND
2001 Sep 06
4

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PDI1394P25EC 전자부품, 판매, 대치품
Philips Semiconductors
1-port 400 Mbps physical layer interface
Preliminary data
PDI1394P25
Name
PLLGND
PLLVDD
Pin Type
Supply
Supply
LQFP
Pin
Numbers
57, 58
LFBGA
Ball
Numbers
D3, E1
56 D1, D4
I/O
RESET
CMOS 5 V tol 53
C1
I
R0
R1
SYSCLK
TEST0
TESTM
Bias 40
41
CMOS
CMOS
CMOS
2
29
27
D5
A4
H2
C8
D7
TPA0+
TPA0–
TPB0+
TPB0–
TPBIAS0
Cable
Cable
Cable
Cable
Cable
37
36
35
34
38
B5
B6
C6
A7
A6
O
I
I
I/O
I/O
I/O
I/O
I/O
XI
Crystal
59
E2
XO 60 E3
Description
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to VDD is provided so only an external
delay capacitor is required for proper power-up operation. For more
information, refer to Section 17.2. This input is otherwise a standard
Schmitt logic input, and can also be driven by an open-drain type driver.
Current setting resistor pins These pins are connected to an external
resistance to set the internal operating currents and cable driver output
currents. A resistance of 6.34 k±1% is required to meet the IEEE
1394–1995 Std. output voltage limits.
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this terminal should be tied to GND.
Test control input. This input is used in manufacturing tests of the
PDI1394P25. For normal use, this input may be tied to VDD (for
compatibility with other vendors’ pin-compatible PHY chips) or to PHY
GND (when a PDI1394P25 is an alternate device).
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
matched and as short as possible to the external load resistors and to
the cable connector.
Twisted-pair bias output. This provides the 1.86 V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. These terminals must be decoupled with a
0.3 µF–1 µF capacitor to ground.
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case and start supplying the external clock
before resetting the PDI1394P25). For more information, refer to
Section 17.5
2001 Sep 06
7

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PDI1394P25EC

1-port 400 Mbps physical layer interface

NXP Semiconductors
NXP Semiconductors

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