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PDF M4Z32-BR00SH Data sheet ( Hoja de datos )
| Número de pieza | M4Z32-BR00SH | |
| Descripción | 5V or 3V NVRAM SUPERVISOR FOR LPSRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M40SZ100Y
M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY
s CONVERT LOW POWER SRAMs INTO
NVRAMs
s 5V OR 3V OPERATING VOLTAGE
s PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
s AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE
s CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40SZ100Y: VCC = 4.5 to 5.5V;
4.20V ≤ VPFD ≤ 4.50V
– M40SZ100W: VCC = 2.7 to 3.6V;
2.55V ≤ VPFD ≤ 2.70V
s RESET OUTPUT (RST) FOR POWER ON
RESET
s 1.25V REFERENCE (for PFI/PFO)
s LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
s OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT® TOP (to be
ordered separately)
s 28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
s BATTERY LOW PIN (BL)
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package*
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
* Contact Local Sales Office
September 2003
Rev. 1.3
1/19
1 page  
Figure 7. Hardware Hookup
Unregulated
Voltage
3.0V, 3.3V or 5V
Regulator
VIN VCC
VCC
VOUT
0.1µF
From Microprocessor
R1
R2
M40SZ100Y
M40SZ100W
E
RSTIN ECON
PFI PFO
VSS
VBAT(1)
RST
BL
M40SZ100Y, M40SZ100W
0.1µF
VCC
1Mb or 4Mb
LPSRAM
E
To Microprocessor NMI
To Microprocessor Reset
To Battery Monitor Circuit
Note: 1. User supplied for the 16-pin package
AI04767
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice reliability. Refer also to the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
TSTG
Storage Temperature (VCC Off)
SNAPHAT
SOIC
–40 to 85
–55 to 125
°C
°C
TSLD(1)
VIO
VCC
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
M40SZ100Y
M40SZ100W
260
–0.3 to VCC +0.3
–0.3 to 7
–0.3 to 4.6
°C
V
V
V
IO Output Current
PD Power Dissipation
20 mA
1W
Note: 1. Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for between 90 to 120
seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
5/19
5 Page 
M40SZ100Y, M40SZ100W
Power-on Reset Output
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40SZ100Y/W has a reset output (RST) pin which
is guaranteed to be low by VPFD (see Table 5,
page 7). This signal is an open drain configuration.
An appropriate pull-up resistor to VCC should be
chosen to control the rise time. This signal will be
valid for all voltage conditions, even when VCC
equals VSS (with valid battery voltage).
Once VCC exceeds the power failure detect volt-
age VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
Figure 12. RSTIN Timing Waveform
Reset Input (RSTIN)
The M40SZ100Y/W provides one independent in-
put which can generate an output reset. The dura-
tion and function of this reset is identical to a reset
generated by a power cycle. Table 7 and Figure 12
illustrate the AC reset characteristics of this func-
tion. Pulses shorter than tRLRH will not generate a
reset condition. RSTIN is internally pulled up to
VCC through a 100kΩ resistor.
RSTIN
RST (1)
tRLRH
tR1HRH
Note: With pull-up resistor
AI04768
Table 7. Reset AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tRLRH(2)
RSTIN Low to RSTIN High
200
ns
tR1HRH(3)
RSTIN High to RST High
40 200 ms
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V (except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. CL = 5pF (see Figure 8, page 6).
11/19
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet M4Z32-BR00SH.PDF ] | |
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