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PDIUSBD12PW 데이터시트 PDF




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부품번호 PDIUSBD12PW 기능
기능 nullUSB interface device with parallel bus
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PDIUSBD12PW 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
PDIUSBD12
USB interface device with parallel bus
Product specification
Supersedes data of 1998 Sep 24
1999 Jan 08
Philips
Semiconductors




PDIUSBD12PW pdf, 반도체, 판매, 대치품
Philips Semiconductors
USB interface device with parallel bus
Product specification
PDIUSBD12
GoodLink
Good USB connection indication is provided through GoodLink
technology. During enumeration, the LED indicator will blink ON
momentarily corresponding to the enumeration traffic. When the
PDIUSBD12 is successfully enumerated and configured, the LED
indicator will be permanently ON. Subsequent successful (with
acknowledgement) transfer to and from the PDIUSBD12 will blink
OFF the LED. During suspend, the LED will be OFF.
This feature provides a user-friendly indicator on the status of the
USB device, the connected hub and the USB traffic. It is a useful
field diagnostics tool to isolate faulty equipment. This feature helps
lower field support and hotline costs.
Memory Management Unit (MMU) and
Integrated RAM
The MMU and the integrated RAM buffer the difference in speed
between USB, running in bursts of 12 Mbits/s and the parallel
interface to the microcontroller. This allows the microcontroller to
read and write USB packets at its own speed.
Parallel and DMA Interface
A generic parallel interface is defined for ease-of-use, speed, and
allows direct interfacing to major microcontrollers. To a
microcontroller, the PDIUSBD12 appears as a memory device with
8-bit data bus and 1 address bit (occupying 2 locations). The
PDIUSBD12 supports both multiplexed and non-multiplexed
address and data bus. The PDIUSBD12 also supports DMA (Direct
Memory Access) transfer which allows the main endpoint (endpoint
2) to directly transfer to and from the local shared memory. Both
single cycle and burst mode DMA transfers are supported.
Example of parallel interface to a dedicated 80C51
In this example, the ALE is permanently tied LOW to signify a
separate address and data bus configuration. The A0 pin of the
PDIUSBD12 connects to any of the 80C51 I/O port. This port
controls command or data phase to the PDIUSBD12. The
multiplexed address and data bus of the 80C51 can now be
connected directly to the data bus of the PDIUSBD12. The address
phase will simply be ignored by the PDIUSBD12. The crystal input
of the 80C51 can be supplied by the CLKOUT output of the
PDIUSBD12.
PDIUSBD12
INT_N
A0
DATA [7:0]
WR_N
RD_N
CLKOUT
CS_N
ALE
80C51
–INTO/P3.2
ANY I/O PORT (e.g. P3.3)
P [0.7:0.0]/AD [7:0]
–WR/P3.6
–RD/P3.7
XTAL1
SV00870
1999 Jan 08
4

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PDIUSBD12PW 전자부품, 판매, 대치품
Philips Semiconductors
USB interface device with parallel bus
Product specification
PDIUSBD12
PINNING
Pin configuration
DATA<0> 1
DATA<1> 2
DATA<2> 3
DATA<3> 4
GND 5
DATA<4> 6
DATA<5> 7
DATA<6> 8
DATA<7> 9
ALE 10
CS_N 11
SUSPEND 12
CLKOUT 13
INT_N 14
28 A0
27 VOUT3.3
26 D+
25 D–
24 VDD
23 XTAL2
22 XTAL1
21 GL_N
20 RESET_N
19 EOT_N
18 DMACK_N
17 DMREQ
16 WR_N
15 RD_N
SV01019
Pin Description
PIN SYMBOL TYPE DESCRIPTION
1 DATA <0>
IO2 Bit 0 of bi-directional data.
Slew-rate controlled.
2 DATA <1>
IO2 Bit 1 of bi-directional data.
Slew-rate controlled.
3 DATA <2>
IO2 Bit 2 of bi-directional data.
Slew-rate controlled.
4 DATA <3>
IO2 Bit 3 of bi-directional data.
Slew-rate controlled.
5 GND
P Ground.
6 DATA <4>
IO2 Bit 4 of bi-directional data.
Slew-rate controlled.
7 DATA <5>
IO2 Bit 5 of bi-directional data.
Slew-rate controlled.
8 DATA <6>
IO2 Bit 6 of bi-directional data.
Slew-rate controlled.
9 DATA <7>
IO2 Bit 7 of bi-directional data.
Slew-rate controlled.
10 ALE
Address Latch Enable. The falling
edge is used to close the latch of the
I
address information in a multiplexed
address/ data bus. Permanently tied
low for separate address/ data bus
configuration.
11 CS_N
I Chip Select (Active Low).
12 SUSPEND I,OD4 Device is in Suspend state.
13 CLKOUT
O2 Programmable Output Clock
(slew-rate controlled).
14 INT_N
OD4 Interrupt (Active Low).
NOTE:
1. O2
OD4
OD8
IO2
O4
: Output with 2 mA drive
: Output Open Drain with 4 mA drive
: Output Open Drain with 8 mA drive
: Input and Output with 2 mA drive
: Output with 4mA drive
PIN SYMBOL TYPE DESCRIPTION
15 RD_N
I Read Strobe (Active Low).
16 WR_N
I Write Strobe (Active Low).
17 DMREQ
O4 DMA Request.
18 DMACK_N I DMA Acknowledge (Active Low).
19 EOT_N
End of DMA Transfer (Active Low).
Double up as Vbus sensing. EOT_N
I is only valid when asserted together
with DMACK_N and either RD_N or
WR_N.
20 RESET_N
21 GL_N
I
OD8
Reset (Active Low and asynchronous).
Built-in Power-On-Reset circuit
present on chip, so pin can be tied
HIGH to VCC.
GoodLink LED indicator (Active Low)
22 XTAL1
I Crystal Connection 1 (6 MHz)
23 XTAL2
O Crystal Connection 2 (6 MHz). If
external clock signal, instead of
crystal, is connected to XTAL1, then
XTAL2 should be floated.
24 VCC
25 D–
P Voltage supply (4.0 – 5.5V).
To operate the IC at 3.3V, supply
3.3V to both VCC and VOUT3.3 pins.
A USB D– data line
26 D+
A USB D+ data line
27 VOUT3.3
28 A0
P 3.3V regulated output. To operate
the IC at 3.3V, supply a 3.3V to both
VCC and VOUT3.3 pins
Address bit. A0=1 selects command
instruction; A0=0 selects the data
I phase. This bit is a don’t care in a
multiplexed address and data bus
configuration and should be tied high.
1999 Jan 08
7

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PDIUSBD12PW

nullUSB interface device with parallel bus

NXP Semiconductors
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