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KB8823 데이터시트 PDF




Samsung에서 제조한 전자 부품 KB8823은 전자 산업 및 응용 분야에서
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부품번호 KB8823 기능
기능 FREQUENCY SYNTHESIZER
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KB8823 데이터시트, 핀배열, 회로
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
INTRODUCTION
The KB8821/22/23 are high performance dual frequency syn-
thesizers with integrated prescalers designed for RF operation
20-TSSOP-225
up to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The KB8821/22/23 contain dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or an 128/129 prescaler(32/33 or
64/65 for the KB8823) and the IF synthesizer adopts an 8/9 or
a 16/17 prescaler.
Using a proprietary digital phase-locked-loop technique, the
KB8821/22/23 have linear phase detector characteristic and
can be used for very stable, low noise local oscillator signal.
Supply voltage can range from 2.7V to 4.0V. The KB8821/22/
23 are now available in a 20-TSSOP/24-QFN package.
ORDERING INFORMATION
FEATURES
Device
Package Tem. Range
• Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)
• Operating voltage range : 2.7 ~ 4.0V
• Selectable power saving mode(Icc=1uA typical @3V)
• Dual modulus prescaler :
KB8821/22
(RF) 64/65 or 128/129
KB8823
KB8821/22/23
(RF) 32/33 or 64/65
(IF) 8/9 or 16/17
• Programmability via serial bus interface
• No dead-zone PFD
• Variable charge pump output current
• High speed lock mode
KB8821/22/23 20-TSSOP-225 -40 ~ +85°C
KB8821/22/23
24-QFN* -40 ~ +85°C
* QFN : Quad Flat Non-leaded(see Addendum).
APPLICATIONS
• Cellular telephone systems : KB8821
• Portable wireless communications : KB8822
(PCS/PCN, cordless)
• Wireless Local Area Networks (W-LANs)
: KB8823
• Other wireless communication systems
BLOCK DIAGRAM
finRF
finRF
+
-
CLOCK
LE
DATA
OSCin
finIF
finIF
+
-
RF
Prescaler
RF
N Counter
Serial Data Control
RF
R Counter
IF
R Counter
IF
Prescaler
IF
N Counter
RF
Phase
Detector
RF CPoRF
Charge
Pump
RF
LD
foLD
Data Out
Multiplexer
foLD
IF
Phase
Detector
IF
LD
IF
Charge
CPoIF
Pump
Figure 1. BLOCK DIAGRAM
99-06-15
1




KB8823 pdf, 반도체, 판매, 대치품
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
PIN DESCRIPTION
Pin No Symbol I / O
1 VDD1 -
2 Vp1 -
3
CPoRF
O
4 GND -
5 finRF I
6 finRF I
7 GND -
8 OSCin I
9 GND -
10 foLD O
11 CLOCK
I
12 DATA
I
13 LE
I
14 GND
15 finIF
-
I
16 finIF
I
17 GND
-
18 CPoIF O
19 Vp2
20 VDD2
-
-
Description
Power supply voltage input for the RF PLL part. VDD1 must equal VDD2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
Power supply voltage input for RF charge pump(VDD1).
Internal RF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
Ground for RF digital blocks.
RF prescaler input. The signal comes from the external VCO.
The complementary input of the RF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
Ground for RF analog blocks.
Reference counter input. TCXO is connected via a coupling capacitor.
Ground for IF digital blocks.
Multiplexed output of the RF/IF programmable counters, the reference
counters, the lock detect signals and the shift registers. The output level is
CMOS level. (see fout Programmable Truth Table)
CMOS clock input. Serial data for the various counters is transfered into the
22-bit shift register on the rising edge of the clock signal.
Binary serial data input. The MSB of CMOS input data is entered first. The
control bits are on the last two bits. CMOS input.
Load enable CMOS input. When LE becomes high, the data in the shift
register is loaded into one of the four latches(by the control bits).
Ground for IF analog blocks.
The complementary input of the IF prescaler. A bypass capacitor must be
placed as close as possible to this pin and be connected directly to the ground
plane. The bypass capacitor is optional with some loss of sensitivity.
IF prescaler input. The signal comes from the external VCO.
Ground for IF digital blocks.
Internal IF charge pump output for connection to an external loop filter whose
filtered output drives an external VCO.
Power supply voltage input for IF charge pump(VDD2)
Power supply voltage input for the IF PLL part. VDD1 must equal VDD2. In
order to reject supply noise, bypass capacitors must be placed as close as
possible to this pin and be connected directly to the ground plane.
99-06-15
4

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KB8823 전자부품, 판매, 대치품
PRELIMINARY SPECIFICATION (V1.5)
FREQUENCY SYNTHESIZER
KB8821/22/23
ELECTRICAL CHARACTERISTICS(VDD=3.0V, VP=3.0V, -40οCTa85οC Unless otherwise specified)
Characteristic
Symbol Test Conditions
Power Supply Voltage
Power Supply
Current
KB8823 RF + IF
KB8823 RF Only
KB8822 RF + IF
KB8822 RF Only
KB8821 RF + IF
KB8821 RF Only
KB882x IF Only
VDD
VP
IDD VDD=2.7V to 4.0V
Power down Current
IPWDN
Digital inputs : CLOCK, DATA and LE
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
High-Level Input Current
IIH
Low-Level Input Current
IIL
Reference Divider Input : OSCin
Input Current
IIHR
IILR
Digital Output : foLD
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
VDD=3.0V
VDD=2.7V to 4.0V
VDD=2.7V to 4.0V
VIH= VDD=4.0V
VIL=0V, VDD=4.0V
VIH= VDD=4.0V
VIL=0V, VDD=4.0V
Iout = -500µA
Iout = +500µA
Min.
2.7
VDD
Typ.
3.0
3.0
5.5
4.0
4.5
3.0
3.5
2.0
1.5
1.0
Max.
4.0
4.0
Unit
V
mA
10 µA
0.7VDD
-1.0
-1.0
0.3VDD
+1.0
+1.0
V
V
µA
µA
-100
+100
µA
µA
VDD-0.4
V
0.4 V
99-06-15
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