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LC11014-241 데이터시트 PDF




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부품번호 LC11014-241 기능
기능 Computer Image Signal Processing Full-Color Gray-Scale Processor
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LC11014-241 데이터시트, 핀배열, 회로
Ordering number: EN 5578
CMOS LSI
LC11014-241
Computer Image Signal Processing
Full-Color Gray-Scale Processor
Overview
The LC11014-241 is a pseudo gray-scale processor for
TFT-LCD panel displays. It allows TFT-LCD panels with
3, 4, 5 or 6-bit input digital drivers to display the equiva-
lent of 16.7 million colors. It can also be used with XGA
panels in 2-pixel parallel input/output mode.
Package Dimensions
unit: mm
3214-SQFP144
[LC11014-241]
Features
• Handles 8 bits of input data (256-level gray scale data)
for each of the RGB colors
• Realizes reduced resolution loss (as compared to dither-
ing techniques) by using intra-frame and inter-frame
error diffusion processing
• Incorporates a new full-coloration algorithm, formerly
best done using computers
• Operating mode selection of outputs for 3, 4, 5, or 6-bit
drivers
• Selectable 2-pixel parallel input/output, serial-input par-
allel-output, and serial input/output operating modes
• 40MHz (parallel input/output), 65 MHz (serial input,
parallel output), or 50MHz (serial input/output) maxi-
mum clock frequency
• Can operate independently of the number of displayed
pixels since internal operation is controlled by the hori-
zontal and vertical synchronization signals.
• Power-save function to stop the internal operation pro-
cessing circuits, and output only the clock, sync signals
and control signals
• Supports 5V input signals at 3.3V supply voltage
SANYO Electric Co., Ltd. Semiconductor Business Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
61297HA (ID) No. 5578—1/13




LC11014-241 pdf, 반도체, 판매, 대치품
LC11014-241
Pin Functions
Symbol
VDD
VSS
GSPMD [0:2]
IOMD [0:1]
VMD
SCLK
DSIFT
Pin No.
9, 18, 29, 37, 43, 49,
54, 60, 68, 73, 90,
109, 126, 144
1, 12, 19, 24, 30, 36,
42, 48, 55, 61, 65,
67, 72, 82, 91, 100,
108, 118, 127, 135
74 to 76
2, 3
77
81
143
I/O
– Supply voltage (+3.3V)
Function
– Ground (0V)
Mode selection signals [0 to 2] for the gray-scale mode. The setting process for the mode selection lines
is described below. GSPMD0 is the LSB and GSPMD2 is the MSB.
Gray-scale mode
01234567
GSPMD0
LHLHLHLH
GSPMD1
L LHHL LHH
GSPMD2
L L L LHHHH
Intra-frame processing Yes Yes Yes Yes
Processing
Inter-frame processing Yes Yes Yes Yes
Yes Yes Yes
No No No
Number of valid input bits
8888
888
I Number of output bits
3456
456
Gray-scale mode
LCD module
0 Operating mode for TFT LCD modules with 3-bit source driver
1 Operating mode for TFT LCD modules with 4-bit source driver
2, 6 Operating mode for TFT LCD modules with 5-bit source driver
3, 7 Operating mode for TFT LCD modules with 6-bit source driver
5
Operating mode for TFT LCD modules with 3-bit source driver that perform
FRC or other inter-frame processing
Do not use gray-scale modes 0 to 3 with TFT LCD modules that perform FRC or other inter-frame
processing.
Input/output mode select pins. The input/output mode selection lines are described below. IOMD0 is the
LSB and IOMD1 is the MSB.
Input/output mode
0123
IOMD0
LHLH
IOMD1
L LHH
Input
Parallel
Serial
Serial
I
Output
Parallel
Parallel
Serial
Reserved
Input/output mode
0
1
2
LCD module
XGA-compatible 2-pixel parallel input interface TFT LCD panels
2-pixel parallel input interface TFT LCD panels (serial input is converted to
parallel internally)
Serial input interface VGA and SVGA TFT LCD panels
I
Gray-scale processing algorithm select pin. The LC11011-141 algorithm is selected when high. Normal
mode is selected when low or open.
I Clock signal input. Data is processed according to this clock signal.
I In input/output mode 1, data is shifted out on both ×D0 and ×D1 when high.
No. 5578—4/13

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LC11014-241 전자부품, 판매, 대치품
LC11014-241
Switching Characteristics at Ta = 0 to +70°C, VSS = 0V, VDD = 3.15 to 3.45V, CL = 15pF
Parameter
SCLK cycle time1
SCLK cycle time2 3
SCLK cycle time4
SCLK high-level pulse width1
SCLK high-level pulse width2 3
SCLK high-level pulse width4
SCLK low-level pulse width1
SCLK low-level pulse width2 3
SCLK low-level pulse width4
HSYNC low-level pulse width
HSYNC high-level pulse width
CLK propagation delay time1
CLK propagation delay time1
CLKB propagation delay time1
CLKB propagation delay time1
CLK propagation delay time2 3
CLK propagation delay time2 3
CLKB propagation delay time2 3
CLKB propagation delay time2 3
CLK propagation delay time4
CLK propagation delay time4
CLKB propagation delay time4
CLKB propagation delay time4
Data setup time
Data hold time
Data output propagation delay time1
Data output propagation delay time2 3
Data output propagation delay time2 3
Data output propagation delay time2 3
Data output propagation delay time2 3
Data output propagation delay time4
Control signal setup time
Control signal hold time
Control signal propagation delay time1
Control signal propagation delay time2 3 4
1. Parallel input, parallel output
2. Serial input, parallel output (1H number of pixels is even)
3. Serial input, parallel output (1H number of pixels is odd)
4. Serial input, serial output
Symbol
Tsclk
Tsclk
Tsclk
Tschw
Tschw
Tschw
Tsclw
Tsclw
Tsclw
Thpw
Tvpw
Tpckh
Tpckl
Tpcbh
Tpcbl
Tpckh
Tpckl
Tpcbh
Tpcbl
Tpckh
Tpckl
Tpcbh
Tpcbl
Tdsu
Tdhd
Tpdata
Tpdt0sl
Tpdt1sl
Tpdt0sh
Tpdt1sh
Ttdatass
Tcsu
Tchd
Tpctl
Tpctlsp
min
25
15.4
20
10
6.2
8
10
6.2
8
2Tsclk
2Tsclk
7
7
6
7
7
8
7
8
7
7
6
8
5
5
8Tsclk + 9
16Tsclk + 9
15Tsclk + 9
15Tsclk + 9
16Tsclk + 9
16Tsclk + 9
5
5
8Tsclk + 8
16Tsclk + 8
typ
11
11
10
12
12
13
12
13
11
11
10
12
8Tsclk + 14
16Tsclk + 15
15Tsclk + 15
15Tsclk + 15
16Tsclk + 15
16Tsclk + 14
8Tsclk + 13
16Tsclk + 13
max
22
22
20
24
24
25
23
26
22
22
20
25
8Tsclk + 28
16Tsclk + 29
15Tsclk + 30
15Tsclk + 29
16Tsclk + 30
16Tsclk + 27
8Tsclk + 24
16Tsclk + 26
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
No. 5578—7/13

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관련 데이터시트

부품번호상세설명 및 기능제조사
LC11014-241

Computer Image Signal Processing Full-Color Gray-Scale Processor

Sanyo
Sanyo

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