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PDF LMX2542 Data sheet ( Hoja de datos )
| Número de pieza | LMX2542 | |
| Descripción | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 2004
LMX2542
PLLatinumTM Cellular and GPS Frequency Synthesizer
System with Integrated VCO
General Description
LMX2542 is a highly integrated, high performance, low
power frequency synthesizer system optimized for Cellular-
CDMA 1xRTT and IS-95 mobile handsets and data systems
with GPS capabilities. Using a proprietary digital phase
locked loop technique, LMX2542 provides very stable, low
noise local oscillator (LO) signals for up and down conver-
sion in wireless communications devices.
LMX2542 includes a Voltage Controlled Oscillator (VCO) for
both the Cellular-CDMA and GPS frequency bands, a loop
filter, and a Fractional-N RF PLL based on a Delta Sigma
(∆Σ) modulator. In concert, these blocks form a closed loop
RF synthesizer system. The RF synthesizer system oper-
ates from 2087.73 MHz to 2155.14 MHz.
LMX2542 includes an Integer-N IF PLL also. For more flex-
ible loop filter designs, the IF PLL includes a 4-level pro-
grammable charge pump. Together with an external VCO
and loop filter, LMX2542 makes a complete closed loop IF
synthesizer system. The default IF frequency is 367.20 MHz.
Serial data is transferred to the device via a three-wire
MICROWIRETM interface (DATA, LE, CLK).
Operating supply voltage ranges from 2.7V to 3.3V.
LMX2542 features low current consumption: 22 mA at 2.8V.
LMX2542 is available in a 28-Pin Leadless Leadframe Pack-
age (LLP).
Features
n Small Size
5.0 mm x 5.0 mm x 0.75 mm 28-Pin LLP
n RF Synthesizer System
Integrated RF VCO
Integrated Loop Filter
Low Spurious, Low Phase Noise Fractional-N RF
PLL Based on 11-Bit ∆Σ modulator
5 kHz Frequency Resolution
Cellular-CDMA LO: 2105.28 MHz to 2155.14 MHz
(Requires an External LO /2 Circuit)
GPS LO: 2087.73 MHz
(Requires an External LO /1.5 Circuit)
n IF Synthesizer System
Integer-N IF PLL
Programmable Charge Pump Current Levels
IF LO: 367.20 MHz
n Supports Various Reference Oscillator Frequencies:
19.20 MHz/ 19.68 MHz
n Low Current Consumption:
22 mA typical at 2.8V
n 2.7V to 3.3V Operation
n RF Digital Filtered Lock Detect Output
n Hardware and Software Powerdown Control
Applications
n Cellular-CDMA 1xRTT and IS-95 Mobile Handsets with
GPS
n Cellular-CDMA 1xRTT and IS-95 Mobile Data Systems
with GPS
Leadless Leadframe Package (LQA28A)
20082411
PLLatinum™, MICROWIRE™ are trademarks of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200824
www.national.com
1 page  
Ordering Information
Model
LMX2542LQX2121
RF Min
Frequency
(MHz)
2087.73
RF Max
Frequency
(MHz)
2155.14
RF Center
Frequency
(MHz)
~2121
IF
Frequency
(MHz)
367.20
LMX2542LQ2121
2087.73
2155.14
~2121
367.20
Part Number Description
Package
Marking
25422121
25422121
Packing
4500 Units
on Tape
and Reel
1000 Units
on Tape
and Reel
20082403
5 www.national.com
5 Page 
1.0 Functional Description
LMX2542 is a highly integrated, high performance, low
power, frequency synthesizer system optimized for Cellular-
CDMA 1xRTT and IS-95 mobile handsets and data systems
with GPS capabilities. Using a proprietary digital phase
locked loop technique, LMX2542 generates very stable, low
noise local oscillator (LO) signals for up and down conver-
sion in wireless communications devices.
LMX2542 includes a Voltage Controlled Oscillator (VCO) for
the Cellular-CDMA and GPS frequency bands, a loop filter,
and a Fractional-N RF PLL based on a ∆Σ modulator which
supports frequency resolutions as low as 5 kHz. In concert,
these blocks form a closed loop RF synthesizer system. The
RF synthesizer system operates from 2087.73 MHz to
2155.14 MHz. The need for external components is limited
to a few passive elements for matching the RF output im-
pedance, and bypass elements for power line stabilization.
The Fractional-N RF PLL (∆Σ modulator architecture) deliv-
ers low spurious thus providing a significant improvement
over other PLL solutions. In addition, the Fractional-N RF
PLL facilitates faster lock times, which reduces power con-
sumption and system set-up time. Furthermore, the RF loop
filter occupies a much smaller area as opposed to the
Integer-N architecture. This allows the RF loop filter to be
embedded into the circuit, thus minimizing the external noise
coupling.
LMX2542 includes an Integer-N IF PLL also. For more flex-
ible loop filter designs, the IF PLL includes a 4-level pro-
grammable charge pump. Together with an external VCO
and loop filter, LMX2542 makes a complete closed loop IF
synthesizer system. The default IF frequency is 367.20 MHz.
The circuit also supports commonly used reference oscillator
frequencies of 19.20 MHz and 19.68 MHz.
1.1 FREQUENCY GENERATION
1.1.1 RF Frequency Selection
The RF synthesizer (Cellular-CDMA) divide ratio can be
calculated using the following equation:
where:
RF_A < RF_B
fRFout :
fOSCin :
RF_A :
20082407
RF VCO output frequency
Reference oscillator frequency
Preset divide ratio of the RF PLL
binary 3-bit swallow counter
(0 ≤ RF_A ≤ 7)
RF_B :
RF_FN :
Preset divide ratio of the RF PLL
binary 4-bit programmable counter
(2 ≤ RF_B ≤ 15)
Preset numerator of the RF PLL
binary 11-bit modulus counter
(0 ≤ RF_FN < 1920 for fOSCin =
19.20 MHz)
(0 ≤ RF_FN < 1968 for fOSCin =
19.68 MHz)
Note: When the FREQ_OFF bit is set to 1, frequencies with
5 kHz resolution can be generated. In the same way outlined
above, the divide ratio for the desired frequency less 5 kHz
should be programmed. When the FREQ_OFF bit (R1[2]) is
set to 1, the programmed frequency will be shifted by +5 kHz
in order to achieve the desired frequency. Refer to Section
2.3.1 for details on how to program the FREQ_OFF bit.
1.1.2 IF Frequency Selection
The IF synthesizer divide ratio can be calculated using the
following equation:
20082409
where:
IF_A < IF_B
fFin :
fOSCin :
IF_A :
IF_B :
IF_R :
IF VCO output frequency
Reference oscillator frequency
Preset divide ratio of the IF PLL
binary 4-bit swallow counter
(0 ≤ IF_A ≤ 15)
Preset divide ratio of the IF PLL
binary 9-bit programmable counter
(1 ≤ IF_B ≤ 511)
Preset divide ratio of the IF PLL
binary 9-bit programmable
reference counter
(2 ≤ IF_R ≤ 511)
From the above equation and with the SPI_DEF bit set to 1,
LMX2542 generates a fixed IF frequency of 367.20 MHz as
follows:
fFin
(MHz)
367.20
IF_B
191
IF_A
4
fOSCin / IF_R
(kHz)
120
11 www.national.com
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LMX2542.PDF ] | |
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