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PDF LRS1331 Data sheet ( Hoja de datos )
| Número de pieza | LRS1331 | |
| Descripción | Stacked Chip 16M Flash Memory and 4M SRAM | |
| Fabricantes | Sharp | |
| Logotipo |  |
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Data Sheet
LRS1331
Stacked Chip
16M Flash Memory and 4M SRAM
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball 8 mm × 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 90 ns
– Operating current (MAX.)
(The current for F-VCC pin and F-VCCW pin):
– Read: 25 mA (tCYCLE = 200 ns)
– Word write: 57 mA
– Block erase: 42 mA
– Standby current (the current for F-VCC pin): 15 µA
(MAX. F-RP ≤ GND ± 0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
PIN CONFIGURATION
72-BALL FBGA
INDEX
– Thirty-one 32K-word main blocks
– Bottom boot location
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM
– Access time (MAX.): 85 ns
– Operating current: 45 mA (MAX.)
– Standby current: 15 µA (MAX.)
– Data retention current: 2 µA (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as
1,048,576 × 16-bit flash memory and 262,144 × 16-bit
static RAM in one package.
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12
A NC NC NC A11 A15 A14 A13 A12 F-GND NC NC NC
B A16 A8 A10 A9 DQ15 S-WE DQ14 DQ7
C
F-WE F-RY/
BY
T1
S-A17 DQ13 DQ6 DQ4 DQ5
D GND F-RP T2 T4 DQ12 S-CE2 S-VCC F-VCC
E F-WP F-VPP F-A19 DQ11 T3 DQ10 DQ2 DQ3
F S-LB S-UB S-OE NC DQ9 DQ8 DQ0 DQ1
G F-A18 F-A17 A7 A6 A3 A2 A1 S-CE1
H NC NC NC A5 A4 A0 F-CE F-GND F-OE NC NC NC
NOTE: All F-GND and S-GND pins are connected on the board.
Two NC pins at the corner are connected.
Figure 1. LRS1331 Pin Configuration
LRS1331-1
Data Sheet
1
1 page  
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 3. Command Definition for Flash Memory1
COMMAND
BUS CYCLES
FIRST BUS CYCLE
REQUIRED OPERATION2 ADDRESS3 DATA3
SECOND BUS CYCLE
OPERATION2 ADDRESS3 DATA3 NOTES
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Word Write
Block Erase and Word
Write Suspend
Block Erase and
Write Resume
Set Block Lock-Bits
Clear Block Lock-Bits
Set Permanent Lock-Bits
1
≥2
2
1
2
2
2
1
1
2
2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
XA FFH
XA 90H Read
XA 70H Read
XA 50H
BA 20H Write
XA 30H Write
WA 40H or 10H Write
XA B0H
XA D0H
BA 60H Write
XA 60H Write
XA 60H Write
IA ID 4
XA SRD
BA
D0H
5
XA D0H
WA WD 5
5
5
BA 01H 6
XA
D0H
6, 7
XA F1H
NOTES:
1. Commands other than those shown in table are reserved by SHARP for future device
implementations and should not be used.
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
IA = Identifier code address;
BA = Address within the block being erased;
WA = Address of memory location to be written;
SRD = Data read from status register;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE or F-CE (whichever goes HIGH first);
ID = Data read from identifier codes.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
6. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands cannot be done.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
Table 4. Identifier Codes
CODES
Manufacture Code
Device Code
Block Lock
Configuration
Block is Unlocked
Block is Locked
Permanent Lock Device is Unlocked
Configuration
Device is Locked
ADDRESS (A0 - A19)
00000H
00001H
BA + 2
BA + 2
00003H
00003H
DATA (DQ0 - DQ7)1
B0H
E9H
DQ0 = 0
DQ0 = 1
DQ0 = 0
DQ0 = 1
NOTES:
1. DQ8 - DQ15 outputs 00H in word mode. DQ1 - DQ7 are reserved for future use.
2. BA selects the specific block lock configuration code to be read. See Figure 3
for the device identifier code memory map.
NOTES
2
2
Data Sheet
5
5 Page 
Stacked Chip (16M Flash & 4M SRAM)
FLASH MEMORY AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input pulse level
Input rise and fall time
Input and Output timing reference level
Output load
CONDITION
0 V to 2.7 V
10 ns
1.35 V
1TTL + CL (50 pF)
Read Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
Read Cycle Time
Address to Output Delay
F-CE to Output Delay*
F-RP HIGH to Output Delay
F-OE to Output Delay*
F-CE to Output in LOW Z
F-CE HIGH to Output in HIGH-Z
F-OE to Output in LOW Z
F-OE HIGH to Output in HIGH-Z
Output Hold from Address, F-CE or F-OE change,
whichever occurs first
SYMBOL
tAVAV
tAVQV
tELQV
tPHQV
tGLQV
tELQX
tEHQZ
tGLQX
tGHQZ
tOH
MIN.
90
0
0
0
MAX.
90
90
600
40
40
15
NOTE: *F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-OE without impact on tELQV.
LRS1331
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet LRS1331.PDF ] | |
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