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PDF LRS1342 Data sheet ( Hoja de datos )
| Número de pieza | LRS1342 | |
| Descripción | Stacked Chip 16M Flash Memory and 2M SRAM | |
| Fabricantes | Sharp | |
| Logotipo |  |
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Data Sheet
LRS1341/LRS1342
Stacked Chip
16M Flash Memory and 2M SRAM
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 100 ns
– Operating current (MAX.):
The current for F-VCC pin
– Read: 25 mA (tCYCLE = 200 ns)
– Word write: 17 mA
– Block erase: 17 mA
– Deep power down current (the current for
F-VCC pin): 10 µA (MAX. F-CE ≥ F-VCC - 0.2 V,
F-RP ≤-0.2 V, F-VPP ≤0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
PIN CONFIGURATION
72-BALL FBGA
INDEX
– Thirty-one 32K-word main blocks
– Top/Bottom boot location versions
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM
– Access time (MAX.): 85 ns
– Operating current (MAX.):
– 45 mA
– 8 mA (tRC, tWC = 1 µs)
– Standby current: 45 µA (MAX.)
– Data retention current: 35 µA (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 × 16-bit flash memory and
131,072 × 16-bit static RAM in one package.
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12
A NC NC NC A11 A15 A14 A13 A12 GND NC NC NC
B A16 A8 A10 A9 DQ15 S-WE DQ14 DQ7
C
F-WE F-RY/
BY
T1
T3 DQ13 DQ6 DQ4 DQ5
D GND F-RP T2 T4 DQ12 S-CE2 S-VCC F-VCC
E F-WP F-VPP F-A19 DQ11 T5 DQ10 DQ2 DQ3
F S-LB S-UB S-OE NC DQ9 DQ8 DQ0 DQ1
G F-A18 F-A17 A7 A6 A3 A2 A1 S-CE1
H NC NC NC A5 A4 A0 F-CE GND F-OE NC NC NC
NOTE: Two NC pins at the corner are connected.
Figure 1. LRS1341/LRS1342 Pin Configuration
LRS1342-1
Data Sheet
1
1 page  
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
CODES
Manufacture Code
Device Code
Table 4. Identifier Codes
ADDRESS
(A0 - A18)
00000H
00001H
LRS1341 DATA
(DQ0 - DQ7)
B0H
48H
LRS1342 DATA
(DQ0 - DQ7)
B0H
49H
WSMS
7
Table 5. Write Protection Alternatives
OPERATION
Block Erase or
Word Write
F-VPP
VIL
> VPPLK
F-RP
X
VIL
VHH
VIH
VIH
F-WP
X
X
X
VIL
VIH
EFFECT
All blocks locked
All blocks locked
All blocks unlocked
Two boot blocks locked
All blocks unlocked
Table 6. Status Register Definition
ESS
6
ES
WWS
VPPS
WWSS
DPS
54321
R
0
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase Status (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = Word Write Status (WWS)
1 = Error in Word Write
0 = Successful Word Write
SR.3 = VPP Status (VPPS)
1 = F-VPP LOW Detect, Operation Abort
0 = F-VPP Okay
SR.2 = Word Write Suspend Status (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = F-WP and/or F-RP Lock Detected,
Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
NOTES:
1. Check RY/BY or SR.7 to determine block erase or word write
completion. SR.6 - SR.0 are invalid while SR.7 = 0.
2. If both SR.5 and SR.4 are ‘1’s after a block erase attempt, an
improper command sequence was entered.
3. SR.3 does not provide a continuous indication of F-VPP level. The
WSM interrogates and indicates the F-VPP level only after Block
Erase or Word Write command sequences. SR.3 is not guaranteed
to report accurate feedback only when F-VPP ≠ VPPH1, VPPH2.
4. The WSM interrogates the F-WP and F-RP only after Block Erase
or Word Write command sequences. It informs the system,
depending on the attempted operation, if the F-WP is not VIH or
F-RP is not VHH.
5. SR.0 is reserved for future use and should be masked out when
polling the status register.
Data Sheet
5
5 Page 
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Write Cycle (F-CE Controlled)1
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write Cycle Time
F-RP HIGH Recovery to F-CE going to LOW
F-WE Setup to F-CE going LOW
F-CE Pulse Width
F-RP VHH Setup to F-CE going HIGH
F-WP VIH Setup to F-CE going HIGH
F-VPP Setup to F-CE going HIGH
Address Setup to F-CE going HIGH2
Data Setup to F-CE going HIGH2
Data Hold from F-CE HIGH
Address Hold from F-CE HIGH
F-WE Hold from F-CE HIGH
F-CE Pulse Width HIGH
F-CE HIGH to F-RY/BY going LOW
Write Recovery before Read
F-VPP Hold from Valid SRD, F-RY/BY HIGH-Z
F-RP VHH Hold from Valid SRD, F-RY/BY HIGH-Z
F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
tAVAV
tPHEL
tWLEL
tELEH
tPHEH
tSHEH
tVPEH
tAVEH
tDVEH
tEHDX
tEHAX
tEHWH
tEHEL
tEHRL
tEHGL
tQVVL
tQVPH
tQVSL
100
10
0
70
100
100
100
50
50
0
0
0
25
0
0
0
0
100
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
during read-only operations. Refer to AC Characteristics for Read Cycle.
2. Refer to the ‘Flash Memory Command Definition’ section for valid AIN and DIN for block erase or word write.
Block Erase and Word Write Performance
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
SYMBOL
PARAMETER
VPP = 2.7 V to 3.6 V VPP = 11.4 V to 12.6 V
MIN. TYP.1 MAX. MIN. TYP.1 MAX.
UNIT
NOTES
tWHQV1
tEHQV1
tWHQV2
tEHQV2
tWHRZ1
tEHRZ1
tWHRZ2
tEHRZ2
Word Write Time 32K-word Block
Word Write Time 4K-word Block
Block Write Time 32K-word Block
Block Write Time 4K-word Block
Block Erase Time 32K-word Block
Block Erase Time 4K-word Bock
Word Write Suspend Latency Time to Read
Erase Suspend Latency Time to Read
55
60
1.8
0.3
1.2
0.5
7.5 8.6
19.3 23.6
15
30
0.6
0.2
0.7
0.5
6.5 7.5
11.8 15
µs
µs
s
s
s
s
µs
µs
2
2
2
2
2
2
NOTES:
1. Reference values at TA = +25°C and VCC = 3.0 V, VPP = 3.0 V.
2. Excludes system-level overhead.
Data Sheet
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LRS1342.PDF ] | |
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