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PEB20550 데이터시트 PDF




Infineon Technologies AG에서 제조한 전자 부품 PEB20550은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 PEB20550 자료 제공

부품번호 PEB20550 기능
기능 ICs for Communications Extended PCM Interface Controller
제조업체 Infineon Technologies AG
로고 Infineon Technologies AG 로고


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PEB20550 데이터시트, 핀배열, 회로
ICs for Communications
Extended Line Card Interface Controller
ELIC®
PEB 20550
PEF 20550
Versions 1.3
User’s Manual 01.96
T2055-0V13-M1-7600




PEB20550 pdf, 반도체, 판매, 대치품
PEB 20550
Table of Contents
Page
1
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.1.1
1.6.1.2
1.6.1.3
1.6.1.4
1.6.1.5
1.6.1.6
1.6.2
1.6.3
1.6.4
1.6.4.1
1.6.4.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
System Integration and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Digital Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Switching, Layer-1 Control, Group Controller Signaling . . . . . . . . . . . . . .25
Decentralized D-Channel Processing, Multiplexed HDLC-Controller. . . . .27
Decentralized D-Channel Processing,
Dedicated HDLC-Controller per Subscriber . . . . . . . . . . . . . . . . . . . . . . .31
Decentralized D-Channel Processing, Multiplexed plus
Dedicated HDLC-Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Central D-Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Mixed D-Channel Processing, Signaling Decentralized,
Packet Data Centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Key Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Analog Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DECT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Adaptation of a DECT System to an Existing PBX . . . . . . . . . . . . . . . . . .38
DECT Line Card Design for an Existing PBX . . . . . . . . . . . . . . . . . . . . . .40
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.5.1
2.2.5.2
2.2.6
2.2.6.1
2.2.6.2
2.2.6.3
2.2.6.4
2.2.6.5
2.2.7
2.2.7.1
2.2.7.2
2.2.7.3
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .41
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Boundary Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
TAP-Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
EPIC®-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Memory Structure and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . . . . . . . .51
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
SACCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
FIFO-Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Semiconductor Group
4
01.96

4페이지










PEB20550 전자부품, 판매, 대치품
PEB 20550
Table of Contents
Page
4.6.28
4.6.29
4.6.30
4.6.31
4.6.32
4.6.33
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.7.6
4.7.7
4.7.8
4.7.9
4.7.10
4.7.11
4.7.12
4.7.13
4.7.14
4.7.15
4.7.16
4.7.17
4.7.18
4.7.19
4.7.20
4.7.21
4.7.22
4.7.23
4.7.24
4.7.25
4.7.26
4.7.27
4.7.28
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
Status Register EPIC®-1 (STAR_E) . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Command Register EPIC®-1 (CMDR_E) . . . . . . . . . . . . . . . . . . . . . . . .156
Interrupt Status Register EPIC®-1 (ISTA_E) . . . . . . . . . . . . . . . . . . . . . .158
Mask Register EPIC®-1 (MASK_E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
Operation Mode Register (OMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Version Number Status Register (VNSR) . . . . . . . . . . . . . . . . . . . . . . . .162
SACCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Receive FIFO (RFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Transmit FIFO (XFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Interrupt Status Register (ISTA_A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . .165
Mask Register (MASK_A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
Extended Interrupt Register (EXIR_A/B) . . . . . . . . . . . . . . . . . . . . . . . . .166
Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Mode Register (MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Channel Configuration Register 1 (CCR1) . . . . . . . . . . . . . . . . . . . . . . .171
Channel Configuration Register 2 (CCR2) . . . . . . . . . . . . . . . . . . . . . . .173
Receive Length Check Register (RLCR) . . . . . . . . . . . . . . . . . . . . . . . . .174
Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Receive Status Register (RSTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
Receive HDLC-Control Register (RHCR) . . . . . . . . . . . . . . . . . . . . . . . .178
Transmit Address Byte 1 (XAD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
Transmit Address Byte 2 (XAD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
Receive Address Byte Low Register 1 (RAL1) . . . . . . . . . . . . . . . . . . . .179
Receive Address Byte Low Register 2 (RAL2) . . . . . . . . . . . . . . . . . . . .180
Receive Address Byte High Register 1 (RAH1) . . . . . . . . . . . . . . . . . . .180
Receive Address Byte High Register 2 (RAH2) . . . . . . . . . . . . . . . . . . .181
Receive Byte Count Low (RBCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Receive Byte Count High (RBCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Transmit Byte Count Low (XBCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
Transmit Byte Count High (XBCH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
Time Slot Assignment Register Transmit (TSAX) . . . . . . . . . . . . . . . . . .183
Time Slot Assignment Register Receive (TSAR) . . . . . . . . . . . . . . . . . .184
Transmit Channel Capacity Register (XCCR) . . . . . . . . . . . . . . . . . . . . .184
Receive Channel Capacity Register (RCCR) . . . . . . . . . . . . . . . . . . . . .185
Version Status Register (VSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Arbiter Mode Register (AMO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
Arbiter State Register (ASTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
Suspend Counter Value Register (SCV) . . . . . . . . . . . . . . . . . . . . . . . . .187
D-Channel Enable Register IOM-Port 0 (DCE0) . . . . . . . . . . . . . . . . . . .188
D-Channel Enable Register IOM-Port 1 (DCE1) . . . . . . . . . . . . . . . . . . .188
D-Channel Enable Register IOM-Port 2 (DCE2) . . . . . . . . . . . . . . . . . . .188
Semiconductor Group
7
01.96

7페이지


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관련 데이터시트

부품번호상세설명 및 기능제조사
PEB2055

ICs for Communications Extended PCM Interface Controller

Infineon Technologies AG
Infineon Technologies AG
PEB2055

(PEB2054 / PEB2055) ICs for Communications

Siemens Semiconductor
Siemens Semiconductor

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