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기능 CMOS Programmable Electrically Erasable Logic Device
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PEEL18CV8T-10 데이터시트, 핀배열, 회로
® International
CMOS
Technology
Commercial/
Industrial
PEEL™ 18CV8 -5/-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s Multiple Speed Power, Temperature Options
- VCC = 5 Volts ±10%
- Speeds ranging from 5ns to 25 ns
- Power as low as 37mA at 25MHz
- Commercial and industrial versions available
s CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
s Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software and PDS-3
programmer
- PLD-to-PEEL JEDEC file translator
Architectural Flexibility
- Enhanced architecture fits in more logic
- 74 product terms x 36 input AND array
- 10 inputs and 8 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear
- Independent output enables
-- 20 Pin DIP/SOIC/TSSOP and PLCC
s Application Versatility
- Replaces random logic
- Super sets PLDs (PAL, GAL, EPLD)
- Enhanced Architecture fits more logic than ordinary
PLDs
General Description
The PEEL18CV8 is a Programmable Electrically Erasable
Logic (PEEL) device providing an attractive alternative to
ordinary PLDs. The PEEL18CV8 offers the performance,
flexibility, ease of design and production practicality needed
by logic designers today.
The PEEL18CV8 is available in 20-pin DIP, PLCC, SOIC
and TSSOP packages with speeds ranging from 5ns to
25ns with power consumption as low as 37mA. EE-Repro-
grammability provides the convenience of instant repro-
gramming for development and reusable production
inventory minimizing the impact of programming changes
or errors. EE-Reprogrammability also improves factory
testability, thus assuring the highest quality possible.
The PEEL18CV8 architecture allows it to replace over 20
standard 20-pin PLDs (PAL, GAL, EPLD etc.). It also pro-
vides additional architecture features so more logic can be
put into every design. ICT’s JEDEC file translator instantly
converts to the PEEL18CV8 existing 20-pin PLDs without
the need to rework the existing design. Development and
programming support for the PEEL18CV8 is provided by
popular third-party programmers and development software.
ICT also offers free PLACE development software and a
low-cost development system (PDS-3).
Figure 1 Pin Configuration
Figure 2 Block Diagram
DIP
I/CLK
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
TSSOP
20 VCC
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
11 I
PLCC
SOIC
1
04-02-004H




PEEL18CV8T-10 pdf, 반도체, 판매, 대치품
® International
CMOS
Technology
PEELTM 18CV8
function as a dedicated input, a dedicated output, or a bi-
directional I/O. Opening every connection on the output
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
The PEEL18CV8 macrocell also provides control over the
feedback path. The input/feedback signal associated with
each I/O macrocell may be obtained from three different
locations; from the I/O input pin, from the Q output of the
flip-flop (registered feedback), or directly from the OR gate
(combinatorial feedback).
Bi-directional I/O
The input/feedback signal is taken from the I/O pin when
using the pin as a dedicated input or as a bi-directional I/O.
(Note that it is possible to create a registered output func-
tion with a bi-directional I/O.)
Combinatorial Feedback
The signal-select multiplexer gives the macrocell the ability
to feedback the output of the OR gate, bypassing the out-
put buffer, regardless of whether the output function is reg-
istered or combinatorial. This feature allows the creation of
asynchronous latches, even when the output must be dis-
abled. (Refer to configurations 5,6,7 and 8 in Figure 5.)
Figure 4 Block Diagram of the PEEL18CV8
I/O Macrocell
Registered Feedback
Feedback also can be taken from the register, regardless of
whether the output function is to be combinatorial or regis-
tered. When implementing a combinatorial output function,
registered feedback allows for the internal latching of states
without giving up the use of the external output.
Design Security
The PEEL18CV8 provides a special EEPROM security bit
that prevents unauthorized reading or copying of designs
programmed into the device. The security bit is set by the
PLD programmer, either at the conclusion of the program-
ming cycle or as a separate step, after the device has been
programmed. Once the security bit is set it is impossible to
verify (read) or program the PEEL until the entire device
has first been erased with the bulk-erase function.
Programming Support
ICT’s JEDEC file translator allows easy conversion of exist-
ing 20 pin PLD designs to the PEEL18CV8, without the
need for redesign. ICT supports a broad range of popular
third party design entry systems, including Data I/O Synario
and Abel, Logical Devices CUPL and others. ICT also
offers (for free) its proprietary PLACE software, an easy-to-
use entry level PC-based software development system.
Programming support includes all the popular third party
programmers; Data I/O, Logical Devices, and numerous
others. ICT also provides a low cost development program-
mer system, the PDS-3.
4 04-02-004H

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PEEL18CV8T-10 전자부품, 판매, 대치품
® International
CMOS
Technology
PEELTM 18CV8
A.C. Electrical Characteristics
Over the operating range 8
Symbol
Parameter
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
Input5 to non-registered output
Input5 to output enable6
Input5 to output disable6
Clock to Output
Clock to comb. output delay
via internal registered feedback
Clock to Feedback
Input5 or feedback setup to clock
Input5 hold after clock
Clock low time, clock high time8
Min clock period Ext (tSC + tCO1)
Internal feedback (1/tSC+tCF)11
External Feedback (1/tCP)11
No Feedback (1/tCL+tCH)11
Asynchronous Reset Pulse Width
Input5 to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers
in clear state
-5 -7 -10/I-10 -15/I-15 -25/I-25
Units
Min Max Min Max Min Max Min Max Min Max
5 7.5 10 15
25 ns
5 7.5 10 15
25 ns
5 7.5 10 15
25 ns
4 7 7 12
15 ns
7.5 10 12 25
35 ns
2.5 3.5
4
8
15
3.5 5
5 12 20
ns
ns
0000
0
ns
3 3.5 5 10 15
ns
7 12 12 24 35
166.7
117.6
111
50
28.5
ns
MHz
133
83.3
83.3
41.6
28.5
MHz
166.7
142.8
100
50
33.3
MHz
5 7.5 10 15 25
5 7.5 10 15
25
ns
ns
5 7.5 10 15
25 ns
5555
5 µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -2.0V
for periods less than 20 ns.
2. VI and VO are not specified for program/verify operation.
3. Test Points for Clock and VCC in tR and tF are referenced at the 10%
and 90% levels.
4. I/O pins are 0V and VCC.
5. “Input” refers to an input pin signal.
6. tOE is measured from input transition to VREF±0.1V, TOD is measured
from input transition to VOH-0.1V or VOL+0.1V; VREF=VL.
7. Capacitances are tested on a sample basis.
8. Test conditions assume: signal transition times of 3ns or less from the
10% and 90% points, timing reference levels of 1.5V (Unless otherwise
specified).
9. Test one output at a time for a duration of less than 1 second.
10. ICC for a typical application: This parameter is tested with the device
programmed as an 8-bit Counter.
11. Parameters are not 100% tested. Specifications are based on initial
characterization and are tested after any design process modification that
might affect operational frequency.
12. Available only for 18CV8 -15/I-15/-25/I-25 grades
13. 24mA available for 18CV8-5/-7. All other speeds are 16mA.
7 04-02-004H

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