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부품번호 | PEEL22CV10A-15 기능 |
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기능 | CMOS Programmable Electrically Erasable Logic Device | ||
제조업체 | ETC | ||
로고 | |||
Commercial/
Industrial
PEEL™ 22CV10A-7/-10/-15/-25
CMOS Programmable Electrically Erasable Logic Device
Features
s High Speed/Low Power
- Speeds ranging from 7ns to 25ns
- Power as low as 30mA at 25MHz
s Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
s Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
General Description
The PEEL™22CV10A is a Programmable Electrically Eras-
able Logic (PEEL™) device providing an attractive alterna-
tive to ordinary PLDs. The PEEL™22CV10A offers the
performance, flexibility, ease of design and production
practicality needed by logic designers today. The
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP
and 28-pin PLCC packages (see Figure 1), with speeds
ranging from 7ns to 25ns and with power consumption as
low as 30mA. EE-reprogrammability provides the conve-
nience of instant reprogramming for development and a
reusable production inventory, minimizing the impact of
programming changes or errors. EE-reprogrammability
s Architectural Flexibility
- 132 product term X 44 input AND array
- Up to 22 inputs and 10 outputs
- Up to 12 configurations per macrocell
- Synchronous preset, asynchronous clear
- Independent output enables
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
s Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Enhanced Architecture fits more logic
than ordinary PLDs
also improves factory testability, thus ensuring the highest
quality possible. The PEEL™22CV10A is JEDEC file com-
patible with standard 22V10 PLDs. Eight additional configu-
rations per macrocell (a total of 12) are also available by
using the “+” software/programming option (i.e.,
22CV10A+). The additional macrocell configurations allow
more logic to be put into every design. Programming and
development support for the PEEL™22CV10A are pro-
vided by popular third-party programmers and develop-
ment software. ICT also offers free PLACE development
software.
Figure 1. Pin Configuration
DIP
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
Figure 2. Block Diagram
PLCC
*Optional extra ground pin for
-7/I-7 speed grade.
SOIC
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PEELTM 22CV10A
enable term will permanently enable the output buffer and
yield a dedicated output. Conversely, if every connection is
intact, the enable term will always be logically false and the
I/O will function as a dedicated input.
Input/Feedback Select
When configuring an I/O macrocell to implement a regis-
tered function (configurations 1 and 2 in Figure 5), the Q
output of the flip-flop drives the feedback term. When con-
figuring an I/O macrocell to implement a combinatorial
function (configurations 3 and 4 in Figure 5), the feedback
signal is taken from the I/O pin. In this case, the pin can be
used as a dedicated input or a bi-directional I/O. (Refer
also to Table 1.)
Additional Macro Cell Configurations
Besides the standard four-configuration macrocell shown in
Figure 5, each PEEL™22CV10A provides an additional
eight configurations that can be used to increase design
flexibility. The configurations are the same as provided by
the PEEL™18CV8 and PEEL™22CV10AZ. However, to
maintain JEDEC file compatibility with standard 22V10
PLDs the additional configurations can only be utilized by
specifying the PEEL™22CV10A+ for logic assembly and
programming. To reference these additional configurations
please refer to the PEEL™22CV10A+ specifications at the
end of this data sheet.
Design Security
The PEEL™22CV10A provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copying of
designs programmed into the device. The security bit is set
by the PLD programmer, either at the conclusion of the pro-
gramming cycle or as a separate step after the device has
been programmed. Once the security bit is set, it is impos-
sible to verify (read) or program the PEEL™ until the entire
device has first been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 24-bit code to be pro-
grammed into the PEEL™22CV10A if the
PEEL™22CV10A+ software option is used. The code can
be read back even after the security bit has been set. The
signature word can be used to identify the pattern pro-
grammed into the device or to record the design revision,
etc.
Figure 4. Block Diagram of the PEEL™ 22CV10A I/O Macrocell.
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Table 6. Absolute Maximum Ratings
Symbol
VCC
VI, VO
IO
TST
TLT
Parameter
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
This device has been designed and tested for the recommended
operating conditions. Proper operation outside of these levels is not
guaranteed. Exposure to absolute maximum ratings may cause per-
manent damage.
Conditions
Ratings
Unit
Relative to Ground
Relative to Ground1
Per pin (IOL, IOH)
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
-65 to + 150
V
V
mA
°C
Soldering 10 seconds
+300
°C
Table 7. Operating Ranges
Symbol
VCC
TA
TR
TF
TRVCC
Parameter
Supply Voltage
Ambient Temperature
Clock Rise Time
Clock Fall Time
VCC Rise Time
Conditions
Commercial
Industrial
Commercial
Industrial
See Note 3
See Note 3
See Note 3
Min
4.75
4.5
0
-40
Max
5.25
5.5
+70
+85
20
20
250
Unit
V
°C
ns
ns
ms
Table 8. D.C. Electrical Characteristics over the recommended operating conditions
Symbol
VOH
VOHC
VOL
VOLC
VIH
VIL
IIL
IOZ
ICC10
CIN7
COUT7
Parameter
Output HIGH Voltage
Output HIGH Voltage - CMOS13
Output LOW Voltage - TTL
Output LOW Voltage - CMOS13
Input HIGH Level
Input LOW Level
Input Leakage Current
Output Leakage Current
VCC Current
(See CR-1 for typical ICC)
Input Capacitance
Output Capacitance
Conditions
VCC = Min, IOH = -4.0mA
VCC = Min, IOH = -10µA
VCC = Min, IOL = 16mA
VCC = Min, IOH = -10µA
VCC = Max, VIN = GND ≤ VIN £ VCC
I/O = High-Z, GND ≤ VO ≤ VCC
VIN = 0V or 3V
f = 25MHz
All outputs disabled4
-7/I-7
-10/I-10
-15/I-15
-25/I-25
TA = 25°C, VCC = 5.0V
@ f = 1 MHz
Min
2.4
VCC - 0.3
2.0
-0.3
Max
0.5
0.15
VCC + 0.3
0.8
±10
±10
90/100
90/100
135/145
30/40
6
12
Unit
V
V
V
V
V
V
µA
µA
mA
pF
pF
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부품번호 | 상세설명 및 기능 | 제조사 |
PEEL22CV10A-10 | CMOS Programmable Electrically Erasable Logic Device | ETC |
PEEL22CV10A-15 | CMOS Programmable Electrically Erasable Logic Device | ETC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |