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PEEL22CV10AZJI-25 데이터시트 PDF




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기능 CMOS Programmable Electrically Erasable Logic Device
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PEEL22CV10AZJI-25 데이터시트, 핀배열, 회로
PEEL™ 22CV10AZ-25
CMOS Programmable Electrically Erasable Logic Device
Features
Ultra Low Power Operation
- VCC = 5 Volts ±10%
- Icc = 10 µA (typical) at standby
- Icc = 2 mA (typical) at 1 MHz
- tPD = 25ns.
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Development/Programmer Support
- Third party software and programmers
- Anachip PLACE Development Software
Architectural Flexibility
- 133 product terms x 44 input AND array
- Up to 22 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Synchronous preset, asynchronous clear
- Independent output enables
- Programmable clock source and polarity
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC
Application Versatility
- Replaces random logic
- Pin and JEDEC compatible with 22V10
- Ideal for power-sensitive systems
General Description
The PEEL™22CV10AZ is a Programmable Electrically Erasable
Logic (PEEL™) device that provides a low power alternative to
ordinary PLDs. The PEEL™22CV10AZ is available in 24-pin
DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 19). A
“zero-power” (100µA max. ICC) standby mode makes the
PEEL™22CV10AZ ideal for power sensitive applications such as
handheld meters, portable communication equipment and lap- top
computers/ peripherals. EE-reprogrammability provides the
convenience of instant reprogramming for development and a
reusable production inventory minimizing the impact of pro-
gramming changes or errors. EE-reprogrammability also
improves factory testability, thus ensuring the highest quality
possible.
Figure 19 Pin Configuration
DIP
I/CLK
I
I
I
I
I
I
I
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
TSSOP
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I
The PEEL™22CV10AZ is JEDEC file compatible with standard
22V10 PLDs. Eight additional configurations per macrocell (a
total of 12) are also available by using the “+” software/program-
ming option (i.e., 22CV10AZ+ & 22CV10AZ++). The additional
macrocell configurations allow more logic to be put into every
device, potentially reducing the design's component count and
lowering the power requirements even further.
Development and programming support for the
PEEL™22CV10AZ is provided by popular third-party program-
mers and development software. Anachip also offers free Win-
PLACE development software.
Figure 19 Block Diagram
PLCC
SOIC
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10




PEEL22CV10AZJI-25 pdf, 반도체, 판매, 대치품
In addition to emulating the four PAL-type output structures
(configurations 3, 4, 9, and 10), The macrocell provides eight
additional configurations. Equivalent circuits for the twelve mac-
rocell configurations are illustrated in Figure 22. These structures
are accessed by specifying the PEEL™22CV10A+ or
PEEL™22CV10A++ option when assembling the equations.
Figure 21 Equivalent Circuits for the Four Con-
figurations of the I/O Macrocell
Table 1. PEEL™22CV10A Macrocell
Configuration Bits
Configuration
# AB
100
210
301
4
Input/Feedback
Select
Register
Feedback
Bi-Directional
I/O
Output Select
Register
Combinatorial
Active Low
Active High
Active Low
Active High
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Under the control of the output enable term, the I/O pin can func-
tion as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will per-
manently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will
always be logically false and the I/O will function as a dedicated
input.
Input/Feedback Select
When configuring an I/O macrocell to implement a registered
function (configurations 1 and 2 in Figure 21), the Q output of the
flip-flop drives the feedback term. When configuring an I/O mac-
rocell to implement a combinatorial output (configurations 3 and
4 in Figure 21), the feedback term is taken from the I/O pin. In this
case, the pin can be used as a dedicated input or a bi-direc- tional
I/O (Refer also to Table 1.)
Programmable Clock Options
A unique feature of the PEEL™22CV10AZ is a programmable
clock multiplexer that allows you to select true or complement
forms of either the input pin or a product-term clock source. This
feature can be accessed by specifying the PEEL™22CV10A++
option when assembling the equations.
When creating a PEEL™ device design, the desired macrocell
configuration is generally specified explicitly in the design file.
When the design is assembled or compiled, the macrocell config-
uration bits are defined in the last lines of the JEDEC program-
ming file.
Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
4/10

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PEEL22CV10AZJI-25 전자부품, 판매, 대치품
Table 1. Absolute Maximum Ratings
This device has been designed and tested for the specified
operating ranges. Improper operation outside of these
levels is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Symbol
Parameter
VCC
VI, VO
IO
TST
TLT
Supply Voltage
Voltage Applied to Any Pin2
Output Current
Storage Temperature
Lead Temperature
Conditions
Relative to Ground
Relative to Ground1
Per Pin (IOL, IOH)
Soldering 10 Seconds
Rating
-0.5 to +7.0
-0.5 to VCC +0.6
±25
-65 to +150
+300
Unit
V
V
mA
oC
oC
Table 2. Operating Range
Symbol
Parameter
VCC Supply Voltage
TA
TR
TF
TRVCC
Ambient Temperature
Clock Rise Time
Clock Fall Time
VCC Rise Time
Commercial
Industrial
Commercial
Industrial
See Note 3.
See Note 3.
See Note 3.
Conditions
Min Max Unit
4.75 5.25 V
4.5 5.5 V
0 +70 oC
-40 +85 oC
20 ns
20 ns
250 ms
Table 3. D.C. Electrical Characteristics Over the operating range (Unless otherwise specified)
Symbol
VOH
VOHC
VOL
VOLC
VIH
VIL
IIL
ISC
ICCS
ICC10
CIN7
COUT7
Parameter
Output HIGH Voltage – TTL
Output HIGH Voltage – CMOS
Output LOW Voltage – TTL
Output LOW Voltage – CMOS
Input HIGH Voltage
Input LOW Voltage
Input and I/O Leakage Current
Output Short Circuit Current
VCC Current, Standby
VCC Current, f=1MHz
Input Capacitance
Output Capacitance
Conditions
VCC = Min, IOH = -4.0 mA
VCC = Min, IOH = -10.0 µA
VCC = Min, IOL = 16.0 mA
VCC = Min, IOL = 10.0 µA
VCC = Max, GND VIN VCC, I/O=High Z
VCC = Max, VO = 0.5V, TA = 25oC
VIN = 0V or VCC, All Outputs disabled4
VIN = 0V or VCC, All Outputs disabled4
TA = 25oC, VCC=5.0V @ f = 1MHz
Min
2.4
VCC-0.3
2.0
-0.3
-30
10 (typ)
2 (typ)
Max
0.5
0.15
VCC+0.3
0.8
±10
-135
100
5
6
12
Unit
V
V
V
V
V
V
µA
mA
µA
mA
pF
pF
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
7/10

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PEEL22CV10AZJI-25

CMOS Programmable Electrically Erasable Logic Device

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