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부품번호 | PEF20542 기능 |
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기능 | 2 Channel Serial Optimized Communication Controller with DMA | ||
제조업체 | Infineon Technologies AG | ||
로고 | |||
전체 30 페이지수
Data Sheet, DS 1, Sep. 2000
SEROCCO-D
2 Channel Serial Optimized
Communication Controller with
DMA
PEB 20542 Version 1.2
PEF 20542 Version 1.2
www.DataSheet4U.com
Datacom
Never stop thinking.
PEB 20542
Revision History:
Previous Version:
Page
(previous
Version)
Page
(current
Version)
34-36
36-38
85 87
218, 226 222, 230
--
268 272
2000-09-14
DS 1
MISTRAL V1.1 Preliminary Data Sheet, 08.99, DS1
Subjects (major changes since last revision)
Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal
’OST’ is multiplexed with ’CTS’ (was vice versa)
corrected HDLC receive address recognition table
Corrected location of TCD interrupt (async/bisync modes only)
in registers ISR0 and IMR0 from bit 7 to bit 2.
removed referneces to Intel Multiplexed Mode
Chapter "Electrical Characteristics" updated with final
characterization results.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
4페이지 PEB 20542
PEF 20542
Table of Contents
Page
4.4.2.3
4.4.3
4.4.4
4.4.4.1
4.4.4.2
4.4.4.3
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.4.1
4.6
4.6.1
4.6.2
4.6.3
Storage of Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Break Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
In-band Flow Control by XON/XOFF Characters . . . . . . . . . . . . . . . 102
Out-of-band Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
BISYNC Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Character Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Signaling System #7 (SS7) Operation . . . . . . . . . . . . . . . . . . . . . . . . . 117
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Channel Specific SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Channel Specific DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6
6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.3.3
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Data Transmission (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Data Reception (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Internal DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Data Transmission (DMA Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . 263
Data Reception (DMA Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Buffer Switched Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.7.1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Data Sheet 7 2000-09-14
7페이지 | |||
구 성 | 총 30 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
PEF2054 | (PEF2054 / PEF2055) ICs for Communications | Siemens Semiconductor |
PEF20542 | 2 Channel Serial Optimized Communication Controller with DMA | Infineon Technologies AG |
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