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부품번호 | PEF22554HT 기능 |
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기능 | Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications | ||
제조업체 | Infineon Technologies AG | ||
로고 | |||
전체 30 페이지수
Delta Sheet
QuadFALC®
DS7, 2002-09-16
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short
Haul Applications
PEF 22554 HT Version 2.1
PEF 22554 E Version 2.1
Preface
This document describes the changes implemented in the QuadFALC® Version 2.1
related to the previous version 1.3. All functions not mentioned in this document remain
unchanged.
QuadFALC® Version 2.1 is a pin-compatible replacement of QuadFALC® Version 1.x.
Severe errata of QuadFALC® Version 1.3 are fixed. For more information please contact
your local sales office.
Organization of this Document
•
www.DataSheet4U.com
•
•
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Chapter 1, Overview
Gives a general description of the product differences to its predecessor.
Chapter 2, Electrical Characteristics
Shows the differences in electrical behavior.
Chapter 2.4, Changed Supply Power Test Conditions T1/J1
Shows the mechanical dimensions of the new BGA package.
Chapter 3, Appendix
Shows a screenshot of the available software tool.
Related Documentation
Data Sheet PEF 22554 Version 2.1
Errata Sheet PEB 22554 Version 1.3
Addendum PEB 22554 Version 1.3
Revision History: Previous Version:
Preliminray Delta Sheet DS 6, 2002-08-19
Major Changes:
“Functional Changes” on Page 2: Additional compare status field (CCR5.6)
“Changed DC Characteristics” on Page 26: Power Supply Currents & LOS Limits,
Delta Sheet
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2002-09-16
1.6 Pinout
QuadFALC®
PEF 22554
Overview
XL1_1/XDOP1/XOID1
VDDX
XL2_1/XDON1/XFM1
TDI
TDO
VDDR
RL1_1/RDIP1/ROID1
RL2_1/RDIN1/RCLKI1
VSSR
VDDC
RCLK1
XPA1
XPB1
XPC1
XPD1
VDDP
VSS
XPA2
XPB2
XPC2
XPD2
RCLK2
TRS
VDDP
MCLK
VSEL
VSSP
VSSR
RL2_2/RDIN2/RCLKI2
RL1_2/RDIP2/ROID2
VDDR
TCK
TMS
XL2_2/XDON2/XFM2
VDDX
XL1_2/XDOP2/XOID2
108
109
112
116
120
124
128
132
136
140
144
1
104
4
100 96 92 88 84
QuadFALC®
PEF 22554 V2.1
8 12 16 20 24
80
28
76
32
73
72
XL1_4/XDOP4/XOID4
VDDX
XL2_4/XDON4/XFM4
SEC/FSC
68 IM
VDDR
RL1_4/RDIP4/ROID4
RL2_4/RDIN4/RCLKI4
64 VSSR
VDDC
ALE
RCLK4
60 XPD4
XPC4
XPB4
XPA4
56 VSS
VDD
XPD3
XPC3
52 XPB3
XPA3
SCLKX4
XDI4
48 SYNC
RCLK3
RES
VSSR
44 RL2_3/RDIN3/RCLKI3
RL1_3/RDIP3/ROID3
VDDR
INT
40 DBW
XL2_3/XDON3/XFM3
VDDX
37 XL1_3/XDOP3/XOID3
36
F0213
Figure 3 Pin Configuration P-TQFP-144-8, Top View
Delta Sheet
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2002-09-16
4페이지 1.7 Pin Description
QuadFALC®
PEF 22554
Overview
Table 1
VSEL
VDDC
VDDP
VSSP
Additional Pin Functions
I + PU
S
Voltage Select
Enables the internal voltage regulator for 3.3 V-only operation
mode if connected to VDD (recommended) or left open.
Disables the internal voltage regulator for dual power supply mode
if connected to VSS.
Positive Power Supply
for the digital core (1.8 V)
These pins can either be positive power supply input or output
depending on the VSEL input condition.
If the VSEL pin is connected to VSS, these pins are inputs and
must both be connected to the same 1.8 V power supply and
require decoupling.
If the VSEL pin is connected to VDD (3.3 V), these pins will both be
1.8 V power supply outputs and must be decoupled to VSS.
Attention: These pins must not be used to supply external
devices.
S Positive Power Supply for the analog PLL (3.3 V)
S Power Supply Ground for the analog PLL (0 V)
A short pin list of the BGA package is given in Table 2. For a complete signal description
refer to the QuadFALC® V2.1 Preliminary Data Sheet.
Table 2
Ball No.
BGA
N12
M12
L13
L12
L14
L11
K13
K14
BGA Pin Assignment
Pin No. Symbol
TQFP
Input(I) Function
Output(O)
Supply(S)
74 A0
I + PU
Address Bus
75 A1
I + PU
Address Bus
76 A2
I + PU
Address Bus
77 A3
I + PU
Address Bus
78 A4
I + PU
Address Bus
79 A5
I + PU
Address Bus
80 A6
I + PU
Address Bus
81 A7
I + PU
Address Bus
Delta Sheet
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2002-09-16
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부품번호 | 상세설명 및 기능 | 제조사 |
PEF22554HT | Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications | Infineon Technologies AG |
PEF22554HT | Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications | Infineon Technologies AG |
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