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PEF3460E 데이터시트 PDF




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부품번호 PEF3460E 기능
기능 Single channel T3/E3 Framer & Line Interface for ATM/ Frame Relay and PPP/IP
제조업체 Infineon Technologies AG
로고 Infineon Technologies AG 로고


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PEF3460E 데이터시트, 핀배열, 회로
Product Overview, DS2, Dec. 2002
TE3-FALC
omT3/E3 Framer & Line Interface for
.cATM, Frame Relay & PPP/IP
UPEF 3460 E, Version 1.2
www.DataSheet4Wired
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PEF3460E pdf, 반도체, 판매, 대치품
TE3-FALC
PEF 3460 E
Table of Contents
Page
4.1.7
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.7
4.8
4.9
4.10
4.11
Transmit Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DS3/E3 Digital Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS3/E3 Overhead, Bitstream and Payload Access Interface . . . . . . . . . . 29
Clock Multiplier Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
System Interface (UTOPIA / POS-PHY / UTOPIA-L2X) . . . . . . . . . . . . . . 30
UTOPIA Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
POS-PHY Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
UTOPIA-L2X Interface Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Slave Accesses (Device Configuration/Control) . . . . . . . . . . . . . . . . . . 33
Master Accesses (8-Bit EPROM Load Function) . . . . . . . . . . . . . . . . . . 33
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General Purpose I/O Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
OCDS and TEST Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Tools and Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Product Overview
4
DS2, 2002-12-10

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PEF3460E 전자부품, 판매, 대치품
TE3-FALC
PEF 3460 E
Overview
0.18 µm, 1.8 V low power core technology
I/Os are 3.3 V tolerant and have 3.3 V driving capability
Package P-BGA-272-4 (27 mm x 27 mm; pitch 1.27 mm)
Full scan path and BIST of on-chip RAMs for production test
Power consumption: ~ 900 mW (typ.)
Analog Interface
Supports clock recovery on B3ZS and HDB3 line coding.
Meets jitter input tolerance according to GR-499-CORE (Cat. 1 & 2), ITU-T G.823,
G.824 and ETSI TBR24.
Meets jitter output requirements according to GR-499-CORE and ETSI TBR24.
Performs jitter attenuation of receive clock when in loop timed mode for terminal
applications in compliance to GR-499-CORE and TBR24.
Pulse shaper meets templates according to ANSI T1.102 & 404, GR-499-CORE,
ITU-T G.703.
Maximum line length up to 1100 ft. (using standard coaxial cable, for example AT&T
728A, 734A or 734D)
Single RC interface to transformer for both T3 and E3.
External line length selection (LBO) is not required
Provides PLL for transmit clock duty cycle correction.
Provides LOS detection for both T3 (ANSI T1.231) and E3 (G.775)
Identical performance to Infineons PEF 3452 TE3-LIU.
DS3/E3 Framer
DS3 M23 framer in accordance with ANSI T1.107 and T1.404.
E3 framer in accordance with G.832 and G.751.
DS3 support for C-Bit Parity operation and clear channel mode.
Detection of OOF, LOF, AIS, RDI/FERF alarms. Counting of OOF events, parity
errors and far end errors as required in ATMF and IETF MIB.
Automatic insertion of RDI/FERF on correct received alarm status. Generation and
insertion of FEBE on received parity errors.
DS3 C-Bit Parity detection by AIC monitoring; counting and processing of the FEAC
and maintenance data link channel.
E3 G.832 TR byte (16 byte Trail Trace) processing and generation. MA byte multi-
frame synchronization, synchronization status nibble extraction and insertion.
Gathers statistics in accordance with RFC 2496 'Managed Objects for DS3/E3
Interface Type'.
Bypass modes supported to bypass both Framer and Cell/Packet processor.
Product Overview
7
DS2, 2002-12-10

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관련 데이터시트

부품번호상세설명 및 기능제조사
PEF3460E

Single channel T3/E3 Framer & Line Interface for ATM/ Frame Relay and PPP/IP

Infineon Technologies AG
Infineon Technologies AG

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