PDF MC-80C32E-30 Data sheet ( Hoja de datos )

Número de pieza	MC-80C32E-30
Descripción	Rad. Tolerant 8-bit ROMless Microcontroller
Fabricantes	ATMEL Corporation
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No Preview Available ! Features • 8032 Pin and Instruction Compatible • Four 8-bit I/O Ports • Three 16-bit Timer/Counters • 256 bytes RAM • Full-duplex UART • Asynchronous Port Reset • 6 Sources, 2 Level Interrupt Structure • 64 Kbytes Program Memory Space • 64 Kbytes Data Memory Space • Power Control Modes • Idle Mode • Power-down Mode • On-chip Oscillator • Operating Frequency: 30 MHz • Power Supply: 4.5V to 5.5V • Temperature Range: Military (-55oC to 125oC) • No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2 • Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019 • Packages: Side Brazed 40-pin, MQFPJ 44-pin • QML Q and V with SMD 5962-00518 • SCC C an B with Specification SCC9521002 Rad. Tolerant 8-bit ROMless Microcontroller 80C32E Description The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit microcontroller. The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6- source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters. The fully static design of the 80C32E reduces system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The 80C32E has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. Rev. 4149M–AERO–06/04 1 1 page 80C32E Idle and Power-down Operation Idle mode allows the interrupt, serial port and timer blocks to continue to operate while the clock of the CPU is gated off. Power-down mode stops the oscillator. Table 1. PCON Register PCON – Power Control Register 765 SMOD - - 4 - 32 GF1 GF0 1 PD 0 IDL Bit Number Bit Mnemonic Description 7 SMOD Double Baud Rate bit Set to select double baud rate in mode 1, 2 or 3. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. General-purpose Flag 3 GF1 Cleared by user for General-purpose usage. Set by user for General-purpose usage. General-purpose Flag 2 GF0 Cleared by user for General-purpose usage. Set by user for General-purpose usage. Power-down mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 000X 0000 Not bit addressable 4149M–AERO–06/04 5 5 Page 80C32E Figure 5. ICC Test Condition, Power-down Mode VCC ICC Reset = Vss after a high pulse during at least 24 clock cycles VCC P0 VCC RST EA (NC) XTAL2 XTAL1 VSS All other pins are disconnected. Figure 6. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCLCH TCLCH = TCHCL = 5ns. 4149M–AERO–06/04 11 11 Page

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