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MC-80C32E-30-E 데이터시트 PDF




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부품번호 MC-80C32E-30-E 기능
기능 Rad. Tolerant 8-bit ROMless Microcontroller
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MC-80C32E-30-E 데이터시트, 핀배열, 회로
Features
8032 Pin and Instruction Compatible
Four 8-bit I/O Ports
Three 16-bit Timer/Counters
256 bytes RAM
Full-duplex UART
Asynchronous Port Reset
6 Sources, 2 Level Interrupt Structure
64 Kbytes Program Memory Space
64 Kbytes Data Memory Space
Power Control Modes
Idle Mode
Power-down Mode
On-chip Oscillator
Operating Frequency: 30 MHz
Power Supply: 4.5V to 5.5V
Temperature Range: Military (-55oC to 125oC)
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019
Packages: Side Brazed 40-pin, MQFPJ 44-pin
QML Q and V with SMD 5962-00518
SCC C an B with Specification SCC9521002
Rad. Tolerant
8-bit ROMless
Microcontroller
80C32E
Description
The 80C32E is a radiation tolerant ROMless version of the 80C52 single chip 8-bit
microcontroller.
The 80C32E retains all the features of the 80C32 with 256 bytes of internal RAM, a 6-
source, 2-level interrupt system, an on-chip oscillator and three 16-bit timer/counters.
The fully static design of the 80C32E reduces system power consumption by bringing
the clock frequency down to any value, even DC, without loss of data.
The 80C32E has 2 software-selectable modes of reduced activity for further reduction
in power consumption. In the idle mode the CPU is frozen while the timers, the serial
port and the interrupt system are still operating. In the power-down mode the RAM is
saved and all other functions are inoperative.
Rev. 4149M–AERO–06/04
1




MC-80C32E-30-E pdf, 반도체, 판매, 대치품
Mnemonic
ALE
PSEN
EA
XTAL1
XTAL2
Type Name and Function
O (I)
Address Latch Enable: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 the oscillator frequency, and can be
used for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
Program Store ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
O activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
I
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations.
I
Crystal 1: Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
O Crystal 2: Output from the inverting oscillator amplifier
4 80C32E
4149M–AERO–06/04

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MC-80C32E-30-E 전자부품, 판매, 대치품
80C32E
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 2. State of Ports During Idle and Power-down Modes
Mode
Program
Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Power-
down
External
External
1
0
1 Floating Port Data Address Port Data
0 Floating Port Data Port Data Port Data
4149M–AERO–06/04
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부품번호상세설명 및 기능제조사
MC-80C32E-30-E

Rad. Tolerant 8-bit ROMless Microcontroller

ATMEL Corporation
ATMEL Corporation

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