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PDF MC-9400A Data sheet ( Hoja de datos )
| Número de pieza | MC-9400A | |
| Descripción | 320 (240)-BIT AC- PDP DRIVER MODULE | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
HYBRID INTEGRATED CIRCUIT
MC-9400A
320 (240)-BIT AC- PDP DRIVER MODULE
DESCRIPTION
The MC-9400A is a PDP driver module that incorporates five 64-bit high breakdown voltage output (150 V, 40 mA)
CMOS driver ICs. It supports 320 outputs in the case of 4-bit parallel input, and 240 outputs in the case of 3-bit parallel
input.
The integrated structure of the MC-9400A, which combines a COB with an aluminum heat sink and an output flexible
printed circuit (FPC) board, enables the easy implementation of heat dissipation measures and high-density mounting.
FEATURES
• Incorporates five µPD16337s with four 16-bit bi-directional shift registers
• Low thermal resistance realized by chip-on-metal structure
• Provided with connector and capacitor for easy mounting on a panel
• Supports output electrode with a narrow pitch through use of a flexible printed circuit board
• Polarity of all driver outputs can be inverted through use of /PC pins
• Supports custom modules
Remark /XXX indicates active low.
ORDERING INFORMATION
Part Number
MC-9400A
Package
COB
The information in this document is subject to change without notice.
Document No. S13787EJ2V0DS00 (2nd edition)
Data Published October 1998 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
© NEC Corporation 1998
1 page  
MC-9400A
TRUTH TABLE
1. Shift register block
Input
R,/L /CLK
H↓
HX
L↓
LX
Output
AB
Input
OutputNote1
Output
Output Note2
Output
Input
Shift register
Execution of right shift
Retain
Execution of left shift
Retain
Notes 1. On a clock rise, the data S57, S58, S59, and S60 are shifted to S61, S62, S63, and S64, and output from B1, B2, B3,
and B4, respectively.
2. On a clock fall, the data S5, S6, S7, and S8 are shifted to S1, S2, S3, and S4, and output from A1, A2, A3, and A4,
respectively.
Remark X= H or L, H= High level, L= Low level
2. Latch block
LE
H
L
/CLK
↓
↓
X
Output state of latch block (/Ln)
Latches the data of Sn and retains the output data
Retains the latch data
Retains the latch data
Remark X= H or L, H= High level, L= Low level
3. Driver block
/Ln
X
X
X
X
BLK
H
H
L
L
/PC Driver output state
H H (all driver outputs : H)
L L (all driver outputs : L)
H Outputs latch data (/Ln)
L Outputs latch data (/Ln) with polarity inverted
Remark X= H or L, H= High level, L= Low level
5
5 Page 
Propagation delay time (/PC → OUT)
tPHL4, tPLH4
/PC 50%
tPHL4
90%
On
MC-9400A
50%
tPLH4
10%
Rise time, Fall time
tTLH, tTHL
On
tTLH
90 %
10%
tTHL
90 %
10%
Maximum clock frequency
FMAX.
CLK2
50%
1/fMAX.
50%
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MC-9400A.PDF ] | |
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