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PDF MC10H161P Data sheet ( Hoja de datos )
| Número de pieza | MC10H161P | |
| Descripción | Binary to 1-8 Decoder( Low ) | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Binary to 1-8 Decoder (Low)
MC10H161
The MC10H161 provides parallel decoding of a three bit binary word to one
of eight lines. The MC10H161 is useful in high–speed multiplexer/demultiplexer
applications.
The MC10H161 is designed to decode a three bit input word to one of eight
output lines. The MC10H161 output will be low when selected while all other
output are high. The enable inputs, when either or both are high, force all
outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal parallel
path delay times found in other decoder designs. These devices are ideally
suited for multiplexer/demultiplexer applications.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 315 mW Typical (same as MECL 10K)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic
Symbol
Rating
Unit
Power Supply (VCC = 0)
Input Voltage (VCC = 0)
Output Current — Continuous
— Surge
VEE
VI
Iout
–8.0 to 0
0 to VEE
50
100
Vdc
Vdc
mA
Operating Temperature Range
Storage Temperature Range — Plastic
— Ceramic
TA
0 to +75
°C
Tstg
–55 to +150
°C
–55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic
Symbol Min Max Min Max Min Max Unit
Power Supply Current
Input Current High
Input Current Low
High Output Voltage
Low Output Voltage
High Input Voltage
Low Input Voltage
AC PARAMETERS
IE
IinH
IinL
VOH
VOL
VIH
VIL
— 84 — 76 —
84
— 465 — 275 — 275
0.5 — 0.5 — 0.3
—
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45
mA
µA
µA
Vdc
Vdc
Vdc
Vdc
Propagation Delay
Data
Enable
tpd ns
0.6 2.0 0.65 2.1 0.7 2.2
0.8 2.3 0.8 2.4 0.9 2.5
Rise Time
Fall Time
tr 0.55 1.7 0.65 1.8 0.7 1.9 ns
tf 0.55 1.7 0.65 1.8 0.7 1.9 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
LOGIC DIAGRAM
E0 2
E1 15
VCC1 = Pin 1
VCC2 = Pin 16
VEE = Pin 8
A7
B9
6 Q0
5 Q1
4 Q2
3 Q3
13 Q4
12 Q5
11 Q6
C 14
10 Q7
TRUTH TABLE
ENABLE
INPUTS
E1 E0
LL
LL
LL
LL
LL
LL
LL
LL
HX
XH
INPUTS
CB A
L LL
L LH
L HL
L HH
HLL
H LH
HHL
H HH
X XX
X XX
OUTPUTS
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L HH H H HH H
H L H H H HH H
H H L H H HH H
H HH L H HH H
H HH H L HH H
H HHHH LHH
H HHHH HL H
H HH H H HH L
H HH H H HH H
H HH H H HH H
DIP
PIN ASSIGNMENT
VCC1 1 16 VCC2
E0 2 15 E1
Q3 3 14 C
Q2 4 13 Q4
Q1 5 12 Q5
Q0 6 11 Q6
A 7 10 Q7
VEE 8
9B
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
3/93
© Motorola, Inc. 1996
2–249
REV 5
1 page | ||
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| PDF Descargar | [ Datasheet MC10H161P.PDF ] | |
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