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MC14001B 데이터시트 PDF




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기능 B-Suffix Series CMOS Gates
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MC14001B 데이터시트, 핀배열, 회로
MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
All Outputs Buffered
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 2.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
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PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
TSSOP–14
DT SUFFIX
CASE 948G
MARKING
DIAGRAMS
14
MC140XXBCP
AWLYYWW
1
14
140XXB
AWLYWW
1
14
14
0XXB
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC140XXB
AWLYWW
1
XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
DEVICE INFORMATION
Device
Description
MC14001B Quad 2–Input NOR Gate
MC14011B
Quad 2–Input NAND Gate
MC14023B Triple 3–Input NAND Gate
MC14025B Triple 3–Input NOR Gate
MC14071B Quad 2–Input OR Gate
MC14073B Triple 3–Input AND Gate
MC14081B
MC14082B
Quad 2–Input AND Gate
Dual 4–Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 1
1
Publication Order Number:
MC14001B/D




MC14001B pdf, 반도체, 판매, 대치품
MC14001B Series
B–SERIES GATE SWITCHING TIMES
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
Symbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Rise Time, All B–Series Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH = (1.35 ns/pF) CL + 33 ns
tTLH = (0.60 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH = (0.40 ns/PF) CL + 20 ns
tTLH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Fall Time, All B–Series Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL = (1.35 ns/pF) CL + 33 ns
tTHL = (0.60 ns/pF) CL + 20 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTHL = (0.40 ns/pF) CL + 20 ns
tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPropagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC14001B, MC14011B only
tPLH, tPHL = (0.90 ns/pF) CL + 80 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.36 ns/pF) CL + 32 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.26 ns/pF) CL + 27 ns
All Other 2, 3, and 4 Input Gates
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.90 ns/pF) CL + 115 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.36 ns/pF) CL + 47 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ8–Input Gates (MC14068B, MC14078B)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.90 ns/pF) CL + 155 ns
tPLH, tPHL = (0.36 ns/pF) CL + 62 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH, tPHL = (0.26 ns/pF) CL + 47 ns
tPLH, tPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ6. The formulas given are for the typical characteristics only at 25_C.
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Min Typ (7.) Max Unit
ns
— 100 200
— 50 100
— 40 80
ns
— 100 200
— 50 100
— 40 80
ns
— 125 250
— 50 100
— 40 80
— 160 300
— 65 130
— 50 100
— 200 350
— 80 150
— 60 110
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
PULSE
GENERATOR
14 VDD
INPUT
*
OUTPUT
CL
7 VSS
*All unused inputs of AND, NAND gates must be connected to VDD.
All unused inputs of OR, NOR gates must be connected to VSS.
20 ns
20 ns
INPUT
tPHL
90%
50%
10%
tPLH
OUTPUT
INVERTING tTHL
tPLH
OUTPUT
NON–INVERTING
tTLH
90%
50%
10%
90%
50%
10%
tTLH
tPHL
tTHL
Figure 1. Switching Time Test Circuit and Waveforms
VDD
0V
VOH
VOL
VOH
VOL
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MC14001B 전자부품, 판매, 대치품
MC14001B Series
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
SINGLE INPUT NAND, AND
5.0 MULTIPLE INPUT NOR, OR
4.0
SINGLE INPUT NOR, OR
3.0 MULTIPLE INPUT NAND, AND
2.0
1.0
0
0 1.0 2.0 3.0 4.0 5.0
Vin, INPUT VOLTAGE (Vdc)
Figure 8. VDD = 5.0 Vdc
SINGLE INPUT NAND, AND
10 MULTIPLE INPUT NOR, OR
8.0
SINGLE INPUT NOR, OR
6.0 MULTIPLE INPUT NAND, AND
4.0
2.0
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)
Figure 9. VDD = 10 Vdc
16
SINGLE INPUT NAND, AND
14 MULTIPLE INPUT NOR, OR
12
SINGLE INPUT NOR, OR
10 MULTIPLE INPUT NAND, AND
8.0
6.0
4.0
2.0
0
0 2.0 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (Vdc)
Figure 10. VDD = 15 Vdc
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Vout VDD
VO
Vout VDD
VO
VO
0
VO
VDD
Vin 0
VDD
Vin
VIL VIH
(a) Inverting Function
VSS = 0 VOLTS DC
VIL VIH
(b) Non–Inverting Function
Figure 11. DC Noise Immunity
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