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PDF MC14007 Data sheet ( Hoja de datos )
| Número de pieza | MC14007 | |
| Descripción | Dual Complementary Pair Plus Inverter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multi–purpose device consists of three
N–channel and three P–channel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulse–shapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4007A or CD4007UB
• This device has 2 outputs without ESD Protection. Anti–static
precautions must be taken.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
Unit
V
V
mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIP–14
P SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
MARKING
DIAGRAMS
14
MC14007UBCP
AWLYYWW
1
14
14007U
AWLYWW
1
TSSOP–14
DT SUFFIX
CASE 948G
14
14
007U
ALYW
SOEIAJ–14
F SUFFIX
CASE 965
1
14
MC14007U
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14007UBCP PDIP–14
2000/Box
MC14007UBD
SOIC–14
55/Rail
MC14007UBDR2 SOIC–14 2500/Tape & Reel
MC14007UBDT TSSOP–14
96/Rail
MC14007UBF SOEIAJ–14 See Note 1.
MC14007UBFEL SOEIAJ–14 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14007UB/D
1 page  
MC14007UB
VDD
0.01 µF
500 µF ID CERAMIC
PULSE
GENERATOR
14
Vin
7 VSS
Vout
CL
20 ns
20 ns
90%
Vin
50%
10%
tPHL
90%
Vout
50%
10%
VDD
VSS
tPLH
VOH
VOL
tTHL tTLH
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
APPLICATIONS
The MC14007UB dual pair plus inverter, which has
access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
DISABLE 3
+ VDD
2
1
11
INPUT 10
DISABLE 6
12 OUTPUT
9
8
7
INPUT
1
0
X
DISABLE
0
0
1
X = Don’t Care
OUTPUT
0
1
OPEN
VDD
14 OUT = A+B•C
13
11
2
10 12 1
B OUTPUT
8
97
5
3
C
4
6
A
Substrates of P–channel devices internally connected to VDD;
Substrates of N–channel devices internally connected to VSS.
Figure 6. AOI Functions Using Tree Logic
Figure 5. 3–State Buffer
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC14007.PDF ] | |
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