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MC14018B 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 MC14018B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 MC14018B 기능
기능 Presettable Divide-By-N Counter
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


MC14018B 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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MC14018B 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Presettable Divide-By-N
Counter
The MC14018B contains five Johnson counter stages which are
asynchronously presettable and resettable. The counters are synchronous,
and increment on the positive going edge of the clock.
Presetting is accomplished by a logic 1 on the preset enable input. Data on
the Jam inputs will then be transferred to their respective Q outputs
(inverted). A logic 1 on the reset input will cause all Q outputs to go to a logic
1 state.
Division by any number from 2 to 10 can be accomplished by connecting
appropriate Q outputs to the data input, as shown in the Function Selection
table. Anti–lock gating is included in the MC14018B to assure proper
counting sequence.
Fully Static Operation
Schmitt Trigger on Clock Input
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPin–for–Pin Replacement for CD4018B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVDD DCSupplyVoltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout Input or Output Voltage (DC or Transient)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎlin, lout Input or Output Current (DC or Transient),
per Pin
– 0.5 to + 18.0
– 0.5 to VDD + 0.5
± 10
V
V
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation, per Package†
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature(8–SecondSoldering)
500
– 65 to + 150
260
mW
_C
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
MC14018B
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
FUNCTIONAL TRUTH TABLE
Preset Jam
Clock Reset Enable Input Qn
0
0
X0
X0
X1
0 X Qn
0 X Dn*
1 01
1 10
X X1
* Dn is the Data input for that stage. Stage 1
has Data brought out to Pin 1.
PIN ASSIGNMENT
Din
JAM 1
JAM 2
Q2
Q1
Q3
JAM 3
VSS
1
2
3
4
5
6
7
8
16 VDD
15 R
14 C
13 Q5
12 JAM 5
11 Q4
10 PE
9 JAM 4
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
MC14018B
81




MC14018B pdf, 반도체, 판매, 대치품
CLOCK
RESET
PRESET ENABLE
JAM 1
JAM 2
TIMING DIAGRAM
(Q5 Connected to Data Input)
JAM 3
JAM 4
JAM 5
Q1
Q2
Q3
Q4
Q5
DON’T CARE
UNTIL PRESET ENABLE
GOES HIGH
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
FUNCTION SELECTION
Counter
Mode
Connect
Data Input
(Pin 1) to:
Comments
Divide by 10
Divide by 8
Divide by 6
Divide by 4
Divide by 2
Q5
Q4
Q3
Q2
No external
components needed.
Q1
Divide by 9
Divide by 7
Divide by 5
Divide by 3
Q5 Q4
Q4 Q3
Q3 Q2
Q2 Q1
Gate package needed
to provide AND
function. Counter
Skips all 1’s state
JAM 1
2
LOGIC DIAGRAM
JAM 2
3
JAM 3
7
JAM 4
9
JAM 5
12
CLOCK 14
DATA 1
RESET 15
PRESET ENABLE 10
MC14018B
84
CLOCK
SHAPER
D SQ
C
RP
D SQ
C
Q
RP
D SQ
C
RP
D SQ
C
RP
D SQ
C
RP
VDD = PIN 16
VSS = PIN 8
54
Q1 Q2
6 11
Q3 Q4
13
Q5
MOTOROLA CMOS LOGIC DATA

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