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MC14027B 데이터시트 PDF




ON Semiconductor에서 제조한 전자 부품 MC14027B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 MC14027B 기능
기능 Dual J-K Flip-Flop
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MC14027B 데이터시트, 핀배열, 회로
MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge−Clocked Flip−Flop Design
Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4027B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
−0.5 to VDD + 0.5
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA Ambient Temperature Range
−55 to +125
°C
Tstg Storage Temperature Range
−65 to +150
°C
TL Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
QA 1
QA 2
CA 3
RA 4
KA 5
JA 6
SA 7
VSS 8
16 VDD
15 QB
14 QB
13 CB
12 RB
11 KB
10 JB
9 SB
MARKING DIAGRAM
16
14027BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 8
1
Publication Order Number:
MC14027B/D




MC14027B pdf, 반도체, 판매, 대치품
MC14027B
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns
Propagation Delay Times**
Clock to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns
Setup Times
Symbol
tTLH,
tTHL
tPLH,
tPHL
tsu
VDD
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Typ
Min (Note 6) Max
100 200
− 50 100
40 80
− 175 350
− 75 150
− 50 100
− 175 350
− 75 150
− 50 100
− 350 450
− 100 200
− 75 150
140 70
50 25
35 17
Hold Times
th
5.0 140 70
10 50 25
15 35 17
Clock Pulse Width
tWH, tWL
5.0
330
165
10 110 55
15 75 38
Clock Pulse Frequency
fcl 5.0 − 3.0 1.5
10 − 9.0 4.5
15 − 13 6.5
Clock Pulse Rise and Fall Time
tTLH, tTHL
5.0
10
15
− 15
− 5.0
− 4.0
Removal Times
Set
trem
5 90 10 −
10 45
5
15 35
3
Reset
5
50 – 30
10 25 – 15 −
15 20 – 10 −
Set and Reset Pulse Width
tWH
5.0 250 125
10 100 50
15 70 35
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Unit
ns
ns
ns
ns
ns
MHz
ms
ns
ns
http://onsemi.com
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