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PDF MC14027BD Data sheet ( Hoja de datos )
| Número de pieza | MC14027BD | |
| Descripción | Dual J-K Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14027B
Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip–flop. These devices may be
used in control, register, or toggle functions.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4027B
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14027BCP
AWLYYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
SOIC–16
D SUFFIX
CASE 751B
16
14027B
AWLYWW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14027B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14027BCP
PDIP–16
2000/Box
MC14027BD
SOIC–16
2400/Box
MC14027BDR2 SOIC–16 2500/Tape & Reel
MC14027BF
SOEIAJ–16 See Note 1.
MC14027BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14027B/D
1 page  
MC14027B
20 ns
J
K
C
tWH
20 ns
90%
50%
10%
20 ns
tsu
20 ns
90%
50%
10%
tsu
90%
50%
10%
tWL
1
VDD
VSS
20 ns
VDD
th VSS
20 ns
VDD
VSS
tPLH
Q
tTLH
fcl
90%
50%
10%
tPHL
tTHL
VOH
VOL
Inputs R and S low.
For the measurement of tWH, I/fcl, and PD
the Inputs J and K are kept high.
Figure 1. Dynamic Signal Waveforms
(J, K, Clock, and Output)
20 ns
SET OR
RESET
90%
tw
CLOCK
20 ns
50%
10%
trem
20 ns
90%
50%
Q or Q
tPLH
tPHL
50%
tw
VDD
VSS
20 ns VDD
10% VSS
VOH
VOL
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
S
J
K
R
C
LOGIC DIAGRAM
(1/2 of Device Shown)
C
C
C
C
C
C
C
C
Q
C
C
Q
http://onsemi.com
5
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC14027BD.PDF ] | |
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