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PDF MC14028BDR2 Data sheet ( Hoja de datos )

Número de pieza MC14028BDR2
Descripción BCD-To-Decimal Decoder Binary-To-Octal Decoder
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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No Preview Available ! MC14028BDR2 Hoja de datos, Descripción, Manual

MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (one–of–ten) decoded output,
while a 3–bit binary input provides a decoded octal (one–of–eight)
code output with D forced to a logic “0”. Expanded decoding such as
binary–to–hexadecimal (one–of–16), etc., can be achieved by using
other MC14028B devices. The part is useful for code conversion,
address decoding, memory selection control, demultiplexing, or
readout decoding.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Positive Logic Design
Low Outputs on All Illegal Input Combinations
Similar to CD4028B.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14028BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14028B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
– 0.5 to +18.0
– 0.5 to VDD + 0.5
Unit
V
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10 mA
PD Power Dissipation,
per Package (Note 3.)
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14028B
AWLYWW
1
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14028BCP
PDIP–16
2000/Box
MC14028BD
SOIC–16
2400/Box
MC14028BDR2 SOIC–16 2500/Tape & Reel
MC14028BF
SOEIAJ–16 See Note 1.
MC14028BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14028B/D

1 page




MC14028BDR2 pdf
MC14028B
APPLICATIONS INFORMATION
Expanded decoding can be performed by using the
MC14028B and other CMOS Integrated Circuits. The
circuit in Figure 2 converts any 4–bit code to a decimal or
hexadecimal code. The accompanying table shows the input
binary combinations, the associated “output numbers” that
go “high” when selected, and the “redefined output
numbers” needed for the proper code. For example: For the
combination DCBA = 0111 the output number 7 is redefined
for the 4–bit binary, 4–bit gray, excess–3, or excess–3 gray
codes as 7, 5, 4, or 2, respectively. Figure 3 shows a 6–bit
binary 1–of–64 decoder using nine MC14028B circuits and
two MC14069UB inverters.
The MC14028B can be used in decimal digit displays,
such as, neon readouts or incandescent projection indicators
as shown in Figure 4.
INPUTS
D C BA
DC B A
MC14028B
Q9 Q0
DC B
MC14028B
Q9
A
Q0
15 – 8 15 – 0
OUTPUT NUMBERS
Figure 2. Code Conversion Circuit and Truth Table
Inputs
Output Numbers
Code and Redefined
Output Numbers
Hexadecimal Decimal
D C B A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000 00000000000000001 0 0
00
000 10000000000000010 1 1
11
001 00000000000000100 2 3
022
001 10000000000001000 3 2 0 3 3
010 00000000000010000 4 7 1 4 4
010 10000000000100000 5 6 2
3
011 00000000001000000 6 4 3 1
4
011 10000000010000000 7 5 4 2
1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 15 5
1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 9 14 6
5
1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 10 12 7 9
6
1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 11 13 8
5
1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 12 8 9 5 6
1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 13 9
677
1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 11
888
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 10
799
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