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PDF MC14053 Data sheet ( Hoja de datos )
| Número de pieza | MC14053 | |
| Descripción | Analog Multiplexers/Demultiplexers | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally–controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
v• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be VSS
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed
CMOS Devices
MAXIMUM RATINGS (Note 1.)
Symbol
Parameter
VDD DC Supply Voltage (Referenced
to VEE, VSS ≥ VEE)
Vin, Vout
Iin
Input or Output Voltage Range
(DC or Transient) (Referen–
ced to VSS for Control Inputs
and VEE for Switch I/O)
Input Current (DC or Transient)
per Control Pin
Value
– 0.5 to +18.0
– 0.5 to VDD + 0.5
± 10
Unit
V
V
mA
ISW Switch Through Current
PD Power Dissipation,
per Package (Note 2.)
± 25 mA
500 mW
TA Ambient Temperature Range
Tstg Storage Temperature Range
TL Lead Temperature
(8–Second Soldering)
– 55 to +125
– 65 to +150
260
°C
°C
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v vhigh–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS, VEE or VDD). Unused outputs must be left open.
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PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC140XXBCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
140XXB
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
0XXB
ALYW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC140XXB
AWLYWW
1
XX = Specific Device Code
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14051B/D
1 page  
MC14051B, MC14052B, MC14053B
IN/OUT
VDD VDD VDD
VEE
OUT/IN
LEVEL
CONVERTED
CONTROL
VDD
IN/OUT
OUT/IN
VEE CONTROL
Figure 1. Switch Circuit Schematic
TRUTH TABLE
Control Inputs
Select
ON Switches
Inhibit C* B A MC14051B MC14052B MC14053B
0 0 0 0 X0 Y0 X0 Z0 Y0 X0
0 0 0 1 X1 Y1 X1 Z0 Y0 X1
0 0 1 0 X2 Y2 X2 Z0 Y1 X0
0 0 1 1 X3 Y3 X3 Z0 Y1 X1
0 1 00
0 1 01
0 1 10
0 1 11
X4
X5
X6
X7
Z1 Y0 X0
Z1 Y0 X1
Z1 Y1 X0
Z1 Y1 X1
1 x x x None
None
None
*Not applicable for MC14052
x = Don’t Care
INH 6
A 10
B9
X0 12
X1 14
X2 15
X3 11
Y0 1
Y1 5
Y2 2
Y3 4
16 VDD
LEVEL
CONVERTER
BINARY TO 1–OF–4
DECODER WITH
INHIBIT
8 VSS 7 VEE
13 X
3Y
Figure 3. MC14052B Functional Diagram
16 VDD
INH 6
A 11
B 10
C9
LEVEL
CONVERTER
BINARY TO 1–OF–8
DECODER WITH
INHIBIT
X0 13
X1 14
X2 15
X3 12
X4 1
X5 5
X6 2
X7 4
8 VSS 7 VEE
3X
Figure 2. MC14051B Functional Diagram
INH 6
A 11
B 10
C9
16 VDD
LEVEL
CONVERTER
BINARY TO 1–OF–2
DECODER WITH
INHIBIT
8 VSS 7 VEE
X0 12
X1 13
Y0 2
Y1 1
Z0 5
Z1 3
14 X
15 Y
4Z
Figure 4. MC14053B Functional Diagram
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5
5 Page 
16
1
e
Z
D
b
0.13 (0.005) M
MC14051B, MC14052B, MC14053B
PACKAGE DIMENSIONS
9
E HE
8
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
LE
M_
Q1
L
DETAIL P
VIEW P
A
c
A1
0.10 (0.004)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
e 1.27 BSC
0.050 BSC
HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0 _ 10 _ 0 _ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 0.78 ––– 0.031
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11
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| PDF Descargar | [ Datasheet MC14053.PDF ] | |
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