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기능 Analog Multiplexers/Demultiplexers
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MC14053B 데이터시트, 핀배열, 회로
MC14051B, MC14052B,
MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers
are digitally−controlled analog switches. The MC14051B effectively
implements an SP8T solid state switch, the MC14052B a DP4T, and
the MC14053B a Triple SPDT. All three devices feature low ON
impedance and very low OFF leakage current. Control of analog
signals up to the complete supply voltage range can be achieved.
Features
Triple Diode Protection on Control Inputs
Switch Function is Break Before Make
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Analog Voltage Range (VDD − VEE) = 3.0 to 18 V
Note: VEE must be VSS
Linearized Transfer Characteristics
Low−noise − 12 nV/Cycle, f 1.0 kHz Typical
Pin−for−Pin Replacement for CD4051, CD4052, and CD4053
For 4PDT Switch, See MC14551B
For Lower RON, Use the HC4051, HC4052, or HC4053
High−Speed CMOS Devices
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD DC Supply Voltage Range
(Referenced to VEE, VSS VEE)
−0.5 to +18.0 V
Vin, Input or Output Voltage Range
−0.5 to VDD + 0.5 V
Vout (DC or Transient) (Referenced to VSS for
Control Inputs and VEE for Switch I/O)
Iin Input Current (DC or Transient)
per Control Pin
+10 mA
ISW Switch Through Current
±25 mA
PD Power Dissipation per Package (Note 1) 500 mW
TA Ambient Temperature Range
−55 to +125
°C
Tstg Storage Temperature Range
−65 to +150
°C
TL Lead Temperature (8−Second Soldering) 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained to
the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
VSS, VEE or VDD). Unused outputs must be left open.
http://onsemi.com
1
SOIC−16
D SUFFIX
CASE 751B
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING DIAGRAMS
16
1405xBG
AWLYWW
1
SOIC−16
16
14
05xB
ALYWG
G
1
TSSOP−16
x
A
WL, L
Y
WW, W
G or G
= 1, 2, or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 14
1
Publication Order Number:
MC14051B/D




MC14053B pdf, 반도체, 판매, 대치품
MC14051B, MC14052B, MC14053B
ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)
Characteristic
Symbol
VDD – VEE
Vdc
Typ (Note 5)
All Types
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (RL = 1 kW)
MC14051
tPLH, tPHL = (0.17 ns/pF) CL + 26.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 11 ns
tPLH, tPHL = (0.06 ns/pF) CL + 9.0 ns
tPLH, tPHL
5.0
10
15
35
15
12
MC14052
tPLH, tPHL = (0.17 ns/pF) CL + 21.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 8.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 7.0 ns
5.0 30
10 12
15 10
MC14053
tPLH, tPHL = (0.17 ns/pF) CL + 16.5 ns
tPLH, tPHL = (0.08 ns/pF) CL + 4.0 ns
tPLH, tPHL = (0.06 ns/pF) CL + 3.0 ns
5.0 25
10 8.0
15 6.0
Inhibit to Output (RL = 10 kW, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
tPHZ, tPLZ,
tPZH, tPZL
5.0
10
15
350
170
140
Max
90
40
30
75
30
25
65
20
15
700
340
280
Unit
ns
ns
ns
ns
MC14052B
5.0 300 600 ns
10 155 310
15 125 250
MC14053B
5.0 275 550 ns
10 140 280
15 110 220
Control Input to Output (RL = 1 kW, VEE = VSS)
MC14051B
tPLH, tPHL
5.0
10
15
ns
360 720
160 320
120 240
MC14052B
5.0 325 650 ns
10 130 260
15 90 180
MC14053B
5.0 300 600 ns
10 120 240
15 80 160
Second Harmonic Distortion
(RL = 10KW, f = 1 kHz) Vin = 5 VPP
− 10 0.07 − %
Bandwidth (Figure 7)
(RL = 50 W, Vin = 1/2 (VDD−VEE) p−p, CL = 50pF
20 Log (Vout/Vin) = − 3 dB)
BW
10
17 − MHz
Off Channel Feedthrough Attenuation (Figure 7)
RL = 1KW, Vin = 1/2 (VDD − VEE) p−p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B
− 10 –50 − dB
Channel Separation (Figure 8)
(RL = 1 kW, Vin = 1/2 (VDD−VEE) p−p,
fin = 3.0 MHz
− 10 –50 − dB
Crosstalk, Control Input to Common O/I (Figure 9)
(R1 = 1 kW, RL = 10 kW
Control tTLH = tTHL = 20 ns, Inhibit = VSS)
− 10 75 − mV
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The formulas given are for the typical characteristics only at 25_C.
5. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
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MC14053B 전자부품, 판매, 대치품
MC14051B, MC14052B, MC14053B
VDD
10 k
VEE = VSS
VDD
KEITHLEY 160
DIGITAL
MULTIMETER
1 kW
RANGE
X-Y
PLOTTER
Figure 11. Channel Resistance (RON) Test Circuit
TYPICAL RESISTANCE CHARACTERISTICS
350 350
300 300
250 250
200 200
150
TA = 125°C
100
25°C
50 - 55°C
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 12. VDD = 7.5 V, VEE = − 7.5 V
700
10
600
150 TA = 125°C
100 25°C
- 55°C
50
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 13. VDD = 5.0 V, VEE = − 5.0 V
350
TA = 25°C
300
10
500 250 VDD = 2.5 V
400 200
300
TA = 125°C
200
25°C
100 - 55°C
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0
Vin, INPUT VOLTAGE (VOLTS)
Figure 14. VDD = 2.5 V, VEE = − 2.5 V
10
150
5.0 V
100 7.5 V
50
0
- 10 - 8.0 - 6.0 - 4.0 - 2.0 0 0.2 4.0 6.0 8.0 10
Vin, INPUT VOLTAGE (VOLTS)
Figure 15. Comparison at 25°C, VDD = −VEE
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