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M58LV064B150ZA1T 데이터시트 PDF




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부품번호 M58LV064B150ZA1T 기능
기능 64 Mbit 4Mb x16 or 2Mb x32 / Uniform Block / Burst 3V Supply Flash Memories
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M58LV064B150ZA1T 데이터시트, 핀배열, 회로
M58LV064A
M58LV064B
64 Mbit (4Mb x16 or 2Mb x32, Uniform Block, Burst)
3V Supply Flash Memories
PRELIMINARY DATA
FEATURES SUMMARY
s WIDE DATA BUS for HIGH BANDWIDTH
– M58LV064A: x16
– M58LV064B: x16/x32
s SUPPLY VOLTAGE
– VDD = 3.0 to 3.6V M58LV064 core supply
– VDDQ = 1.8 to VDD for I/O Buffers
s SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read
– Pipelined Synchronous Burst Read
– Asynchronous Random Read
– Asynchronous Address Latch Controlled
Read
– Page Read
s ACCESS TIME
– Synchronous Burst Read up to 66MHz
– Asynchronous Page Mode Read 150/25ns
– Random Read 150ns
s PROGRAMMING TIME
– 16 Word or 8 Double-Word Write Buffer
– 12µs Word effective programming time
s 64 UNIFORM 64 KWord MEMORY BLOCKS
s BLOCK PROTECTION/ UNPROTECTION
s PROGRAM and ERASE SUSPEND
s OTP SECURITY AREA
s COMMON FLASH INTERFACE
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code M58LV064A: 0015h
– Device Code M58LV064B: 0014h
Figure 1. Packages
TSOP56 (N)
14 x 20mm
TBGA
TBGA64 (ZA)
10 x 13mm
TBGA
TBGA80 (ZA)
10 x13mm
December 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M58LV064B150ZA1T pdf, 반도체, 판매, 대치품
M58LV064A, M58LV064B
Table 12. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 37
Table 18. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 37
Figure 14. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 19. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 15. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 39
Figure 16. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled. . . . . . 39
Table 20. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable
Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 17. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 41
Figure 18. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 41
Table 21. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable
Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 19. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 20. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 44
Table 22. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . 47
Table 24. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data 47
Figure 23. TBGA64 - 10x13mm, 8 x 8 ball array 1mm pitch, Package Outline . . . . . . . . . . . . . . . 48
Table 25. TBGA64 - 10x13mm, 8 x 8 ball array, 1 mm pitch, Package Mechanical Data . . . . . . . 48
Figure 24. TBGA80 - 10x13mm, 8 x 10 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . 49
Table 26. TBGA80 - 10x13mm, 8 x 10 ball array, 1mm pitch, Package Mechanical Data . . . . . . 49
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 27. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 28. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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M58LV064B150ZA1T 전자부품, 판매, 대치품
Figure 2. Logic Diagram
VDD VDDQ
22
A1-A22
VPP
W
E
G
RP
L
B
K
WORD(1)
16
DQ0-DQ15
16
DQ16-DQ31(1)
M58LV064A
M58LV064B
RB
R
VSS VSSQ
Note: 1. M58LV064B only.
AI03223b
M58LV064A, M58LV064B
Table 1. Signal Names
A1 Address Input (x16 Bus Width only)
A2-A22
Address inputs
DQ0-DQ15 Data Inputs/Outputs
DQ16-DQ31
Data Inputs/Outputs (x32 Bus Width of
M58LV064B only)
B Burst Address Advance
E Chip Enable
G Output Enable
K Clock
L Latch Enable
R Valid Data Ready
RB Ready/Busy
RP Reset/Power-Down
VPP Program/Erase Enable
W Write Enable
WORD
Word Organization (M58LV064B only)
VDD Supply Voltage
VDDQ
Input/Output Supply Voltage
VSS Ground
VSSQ
Input/Output Ground
NC Not Connected Internally
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관련 데이터시트

부품번호상세설명 및 기능제조사
M58LV064B150ZA1T

64 Mbit 4Mb x16 or 2Mb x32 / Uniform Block / Burst 3V Supply Flash Memories

ST Microelectronics
ST Microelectronics

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