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M58MR016C PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 M58MR016C
기능 16 Mbit 1Mb x16 / Mux I/O / Dual Bank / Burst 1.8V Supply Flash Memory
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M58MR016C 데이터시트, 핀배열, 회로
M58MR016C
M58MR016D
16 Mbit (1Mb x16, Mux I/O, Dual Bank, Burst)
1.8V Supply Flash Memory
PRELIMINARY DATA
s SUPPLY VOLTAGE
– VDD = VDDQ = 1.7V to 2.0V for Program,
Erase and Read
– VPP = 12V for fast Program (optional)
s MULTIPLEXED ADDRESS/DATA
s SYNCHRONOUS / ASYNCHRONOUS READ
– Burst mode Read: 40MHz
– Page mode Read (4 Words Page)
– Random Access: 100ns
s PROGRAMMING TIME
– 10µs by Word typical
– Two or four words programming option
s MEMORY BLOCKS
– Dual Bank Memory Array: 4/12 Mbit
– Parameter Blocks (Top or Bottom location)
s DUAL OPERATIONS
– Read within one Bank while Program or
Erase within the other
– No delay between Read and Write operations
s PROTECTION/SECURITY
– All Blocks protected at Power-up
– Any combination of Blocks can be protected
– 64 bit unique device identifier
– 64 bit user programmable OTP cells
– One parameter block permanently lockable
s COMMON FLASH INTERFACE (CFI)
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M58MR016C: 88DEh
– Bottom Device Code, M58MR016D: 88E0h
FBGA
TFBGA48 (ZC)
10 x 4 ball array
Figure 1. Logic Diagram
VDD VDDQ VPP
4
A16-A19
W
E
G
RP
WP
L
K
16
ADQ0-ADQ15
M58MR016C
M58MR016D
WAIT
BINV
VSS
AI05228
August 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M58MR016C pdf, 반도체, 판매, 대치품
M58MR016C, M58MR016D
The architecture includes a 128 bit Protection reg-
ister that is divided into two 64 bit segments. In the
first one is written a unique device number, while
the second one is programmable by the user. The
user programmable segment can be permanently
protected programming the bit 1 of the Protection
Lock Register (see protection register and Securi-
ty Block). The parameter block (# 0) is a security
block. It can be permanently protected by the user
Table 3. Bank Size and Sectorization
Bank Size
Bank A
4 Mbit
Bank B
12 Mbit
programming the bit 2 of the Protection Lock Reg-
ister.
Block protection against Program or Erase pro-
vides additional data security. All blocks are pro-
tected and unlocked at Power-up. Instructions are
provided to protect or un-protect any block in the
application. A second register locks the protection
status while WP is low (see Block Locking descrip-
tion).
Parameter Blocks
8 blocks of 4 KWord
-
Main Blocks
7 blocks of 32 KWord
24 blocks of 32 KWord
Figure 3. Memory Map
Bank B
Top Boot Block
Address lines A19-A0
000000h
007FFFh
512 Kbit or
32 KWord
0B8000h
0BFFFFh
0C0000h
0C7FFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Bank A
0F0000h
0F7FFFh
0F8000h
0F8FFFh
512 Kbit or
32 KWord
64 Kbit or
4 KWord
0FF000h
0FFFFFh
64 Kbit or
4 KWord
Total of 24
Main Blocks
Bottom Boot Block
Address lines A19-A0
000000h
000FFFh
64 Kbit or
4 KWord
Bank A
Total of 7
Main Blocks
007000h
007FFFh
008000h
00FFFFh
64 Kbit or
4 KWord
512 Kbit or
32 KWord
Total of 8
Parameter
Blocks
Bank B
038000h
03FFFFh
040000h
047FFFh
0F8000h
0FFFFFh
512 Kbit or
32 KWord
512 Kbit or
32 KWord
512 Kbit or
32 KWord
Total of 8
Parameter
Blocks
Total of 7
Main Blocks
Total of 24
Main Blocks
AI05230
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M58MR016C 전자부품, 판매, 대치품
M58MR016C, M58MR016D
DEVICE OPERATIONS
The following operations can be performed using
the appropriate bus cycles: Address Latch, Read
Array (Random, and Page Modes), Write com-
mand, Output Disable, Standby, reset/Power-
down and Block Locking. See Table 4.
Address Latch. In asynchronous operation, the
address is latched on the rising edge of L input. In
burst mode the address is latched either on the ris-
ing edge of L or on the first rising/falling edge of K
(depending on configuration settings) when L is
low.
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
Table 4. User Bus Operations (1)
Operation
EG
W
Address Latch
VIL VIH VIH
Write
VIL VIH VIL
Output Disable
VIL VIH VIH
Standby
VIH X
X
Reset / Power-down
X
X
X
Block Locking
Note: 1. X = Don’t care.
VIL
X
X
nature, the Status Register, the CFI, the Block
Protection Status, the Read Configuration Regis-
ter status and the Protection Register.
Read operation of the Memory Array may be per-
formed in asynchronous page mode or synchro-
nous burst mode. In asynchronous page mode
data is internally read and stored in a page buffer.
The page has a size of 4 words and is addressed
by ADQ0 and ADQ1 address inputs.
According to the device configuration the following
Read operations: Electronic Signature - Status
Register - CFI - Block Protection Status - Read
Configuration Register Status - Protection Regis-
ter must be accessed as asynchronous read or as
single synchronous read (see Figure 4).
L
VIL
(rising edge)
VIH
VIH
X
X
X
RP
VIH
VIH
VIH
VIH
VIL
VIH
WP ADQ15-ADQ0
VIH Address Input
VIH Data Input
VIH Hi-Z
X Hi-Z
X Hi-Z
VIL X
Table 5. Read Electronic Signature (AS and Read CFI instructions) (1)
Code
Device E G W ADQ1 (3) ADQ0 (3)
Manufacturer Code
VIL VIL VIH VIL
Device Code
M58MR016C
M58MR016D
VIL
VIL
VIL VIH
VIL VIH
VIL
VIL
Note: 1. Addresses are latched on the rising edge of L input.
2. EA means Electronic Signature Address (see Read Electronic Signature)
3. Value during address latch.
VIL
VIH
VIH
Other
Address (2)
EA (2)
EA (2)
EA (2)
ADQ15-0
0020h
88DEh
88E0h
Table 6. Read Block Protection (AS and Read CFI instructions) (1)
Block Status
E
G
W
ADQ1 (3) ADQ0 (3)
Other
Address
Protected and unlocked
VIL VIL VIH VIH VIL BA (4)
Unprotected and unlocked
VIL VIL VIH VIH VIL BA (4)
Protected and locked
VIL VIL VIH VIH VIL BA (4)
Unprotected and locked (2)
VIL VIL VIH VIH VIL BA (4)
Note: 1. Addresses are latched on the rising edge of L input.
2. A locked block can be unprotected only with WP at VIH.
3. Value during address latch.
4. BA means Block Address. First cycle command address should indicate the bank of the block address.
ADQ15-0
0001
0000
0003
0002
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부품번호상세설명 및 기능제조사
M58MR016C

16 Mbit 1Mb x16 / Mux I/O / Dual Bank / Burst 1.8V Supply Flash Memory

ST Microelectronics
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M58MR016D

16 Mbit 1Mb x16 / Mux I/O / Dual Bank / Burst 1.8V Supply Flash Memory

ST Microelectronics
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