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M59BW102N 데이터시트 PDF




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부품번호 M59BW102N 기능
기능 1 Mbit 64Kb x16 / Burst Low Voltage Flash Memory
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M59BW102N 데이터시트, 핀배열, 회로
M59BW102
1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory
PRELIMINARY DATA
s 2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
s SEQUENTIAL CYCLE TIME: 25ns
s RANDOM ACCESS TIME
s PROGRAMMING TIME: 10µs typical
s INTERLEAVED ACCESS TIME: 16ns
s CONTINUOUS MEMORY INTERLEAVING
– Unlimited Linear Access Data Output
s PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Word-by-Word
– Status Register bits
s LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
s 100,000 PROGRAM/ERASE CYCLES
s 20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: C1h
DESCRIPTION
The M59BW102 is a non-volatile memory that may
be erased electrically at the chip level and pro-
grammed in-system on a Word-by-Word basis us-
ing only a single 3V VCC supply. For Program and
Erase operations the necessary high voltages are
generated internally. The device can also be pro-
grammed in standard programmers.
The device can be programmed and erased over
100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature, Programming and
Chip Erase are written to the device in cycles of
commands to a Command Interface using stan-
dard microprocessor write timings. The
M59BW102 features an interleaved access mo-
dality which allows extremely fast access time.
The device is offered in TSOP40 (10 x 14mm)
package.
TSOP40 (N)
10 x 14mm
Figure 1. Logic Diagram
VCC
16
A0-A15
16
DQ0-DQ15
W
E M59BW102
G
ALE
VSS
AI02763B
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M59BW102N pdf, 반도체, 판매, 대치품
M59BW102
Table 5. Commands
Hex Code
Command
00h Invalid/Reserved
10h Chip Erase Confirm
20h Reserved
80h Set-up Erase
90h Read Electronic Signature
A0h Program
F0h Read Array/Reset
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G and ALE are both High the out-
puts are High impedance.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Address Latch Enable (ALE). This input con-
trols the latching of address for reading. When
pulsed, the device operates in the random or non
linear access mode.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
DEVICE OPERATIONS
See Tables 3 and 4.
Read (Non Linear Access Mode and Linear Ac-
cess Cycle). The device is internally organized in
two memory banks (named Even and Odd bank).
A0 address bit is asserted as "priority" bit, so that
when A0 = 0 the even bank is the current memory
array under selection and the odd bank is masked.
When A0 = 1 the odd bank is the current array un-
der selection and even bank is masked.
To begin a random (or Non Linear) access mode
(NLA), ALE is pulsed high and E is asserted low.
Two internal 15 bit counters store the current ad-
dress for the odd and even banks and increment
alternatively, under the priority bit control, during
each subsequent cycle called sequential (or Lin-
ear) address cycle (LA). The linear cycle (LA) can
be terminated if a new NLA starts or if E is assert-
ed high, putting the device in stand-by mode. In
this last case the linear cycle can be resumed if E
is asserted low again and ALE is low.
During the LA mode all the memory can be swept,
as there is no physical limits to the linear access
output. When the last address of the memory is
reached by the counters they start again from the
first memory address and continue. The
M59BW102 will provide data output during the LA
cycle determined by G signal.
Each time ALE signal is pulsed and G signal is
High, while the current address is loaded into the
counters, the output buffers are put in Hi-Z condi-
tion and remain in this condition until the first new
valid data comes. The M59BW102 operation in LA
and NLA modes is explained in Figure 3 and the
block diagram is shown in Figure 4.
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Address Latch Enable (ALE) is high,
Chip Enable E is Low and Write Enable W is Low
with Output Enable G High. Addresses are latched
on the falling edge of W or E whichever occurs
last. Commands and Input Data are latched on the
rising edge of W or E whichever occurs first.
Output Disable. The data outputs are high im-
pedance when the Output Enable G and the Ad-
dress Latch Enable (ALE) are both High with Write
Enable W High.
Standby. The memory is in standby when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the standby level and
the outputs are high impedance, independent of
the Output Enable G, the Address Latch Enable
(ALE) or the Write Enable W inputs.
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for
STMicroelectronics is 20h, the device code is C1h.
These codes allow programming equipment or ap-
plications to automatically match their interface to
the characteristics of the M59BW102. The Elec-
tronic Signature is output by a Read operation
when the voltage applied to A9 is at VID and ad-
dress inputs A1 is Low. The manufacturer code is
output when the Address input A0 is Low and the
device code when this input is High. Other Ad-
dress inputs are ignored. The codes are output on
DQ0-DQ7.
The Electronic Signature can also be read, without
raising A9 to VID, by giving the memory the In-
struction AS. The codes are output on DQ0-DQ7
with DQ8-DQ15 at 00h.
Table 6. Polling and Toggle Bits
Mode
DQ7
DQ6
Program
DQ7
Toggle
Erase
0 Toggle
DQ2
1
Toggle
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M59BW102N 전자부품, 판매, 대치품
M59BW102
Table 7. Instructions (1)
Mne.
Instr.
Cyc.
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc.
RD (2,4)
Read/Reset
Memory Array
Addr. (3,6)
1+
Data
Addr. (3,6)
3+
Data
X
F0h
555h
AAh
Read Memory Array until a new write cycle is initiated.
2AAh
55h
X Read Memory Array until a new write
F0h cycle is initiated.
AS (4) Auto Select
Addr. (3,6)
3+
Data
555h
AAh
2AAh
55h
555h
90h
Read Electronic Signature until a new
write cycle is initiated. See Note 5.
PG Program
Addr. (3,6) 555h
4
Data
AAh
2AAh
55h
555h
A0h
Program
Address
Program
Data
Read Data Polling or Toggle
Bit until Program completes.
CE Chip Erase
Addr. (3,6) 555h
6
Data
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Note 7
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of 10µs is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation.
3. X = Don't Care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the com-
mand cycles.
5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
code.
6. For Coded cycles address inputs A11-A16 are don't care.
7. Read Data Polling, Toggle bits until Erase completes.
data. DQ6 will toggle following toggling of either G,
or E when G is low. The operation is completed
when two successive reads yield the same output
data. The next read will output the bit last pro-
grammed or a ’1’ after erasing. The toggle bit DQ6
is valid only during P/E.C. operations, that is after
the fourth W pulse for programming or after the
sixth W pulse for Erase. See Figure 13 for Toggle
Bit flowchart and Figure 14 for Toggle Bit wave-
forms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. During Chip Erase a
read operation will cause DQ2 to toggle since chip
is being erased. DQ2 will be set to ’1’ during pro-
gram operation and when erase is complete.
Error Bit (DQ5). This bit is set to ’1’ by the P/E.C.
when there is a failure of programming or chip
erase that results in invalid data in the memory. In
case of an error in program, the chip must be dis-
carded. The DQ5 failure condition will also appear
if a user tries to program a ’1’ to a location that is
previously programmed to ’0’. The error bit resets
after a Read/Reset (RD) instruction. In case of
success of Program or Erase, the error bit will be
set to ’0’.
Erase Timer Bit (DQ3). This bit is set to ’0’ by the
P/E.C. when the Erase command has been en-
tered to the Command Interface and it is awaiting
the Erase start. When the erase timeout period is
finished, after 50µs to 120µs, DQ3 returns to '1'.
Coded Cycles
The two Coded cycles unlock the Command Inter-
face. They are followed by an input command or a
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy-
cles consist of writing the data 55h at address
2AAh. Address lines A0 to A10 are valid; other ad-
dress lines are 'don't care'. The Coded cycles hap-
pen on first and second cycles of the command
write or on the fourth and fifth cycles.
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