Datasheet.kr   

M5M4V4265CTP-5 데이터시트 PDF




Mitsubishi에서 제조한 전자 부품 M5M4V4265CTP-5은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M5M4V4265CTP-5 자료 제공

부품번호 M5M4V4265CTP-5 기능
기능 EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
제조업체 Mitsubishi
로고 Mitsubishi 로고


M5M4V4265CTP-5 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

M5M4V4265CTP-5 데이터시트, 핀배열, 회로
MITMSUITBSIUSHBISLHSIIsLSIs
M5M4V4265CJM,5TMP4V-452,6-56C,J-,7TP,--55,-S6,,--76,-5SS,,--67SS,-7S
EDOED(HOY(PHEYRPPEARGPEA)GMEO) DMEO4D1E9431094-3B0I4T-B(2IT62(124642-1W44O-WRDORBDY 1B6Y-B1I6T-)BDITY)NDAYMNIACMRICAMRAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
FEATURES
Type name
RAS
CAS Address
access access access
time time time
OE Cycle
access
time
time
Power
dissipa-
tion
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
M5M4V4265CXX-5,-5S 50
13
25 13
90 408
M5M4V4265CXX-6,-6S 60 15 30 15 110 363
M5M4V4265CXX-7,-7S 70 20 35 20 130 333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level
1.8mW (Max)
CMOS Input level
360µW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S
486mW (Max)
M5M4V4265CXX-6,-6S
432mW (Max)
M5M4V4265CXX-7,-7S
396mW (Max)
Self refresh capability *
Self refresh current
100µA (Max)
Extended refresh capability
Extended refresh current
100µA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A0~A8)
512 refresh cycles every 128ms (A0~A8) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN DESCRIPTION
Pin name
A0~A8
DQ1~DQ16
RAS
LCAS
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
UCAS
Upper byte control
column address strobe input
W Write control input
OE Output enable input
VCC Power supply (+3.3V)
VSS Ground (0V)
1
M5M4V4265CJ,TP-5,-5S:under development
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
NC 11
NC 12
W 13
RAS 14
NC 15
A0 16
A1 17
A2 18
A3 19
(3.3V)VCC 20
40 VSS(0V)
39 DQ16
38 DQ15
37 DQ14
36 DQ13
35 VSS(0V)
34 DQ12
33 DQ11
32 DQ10
31 DQ9
30 NC
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21 VSS(0V)
Outline 40P0K (400mil SOJ)
(3.3V)VCC 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
(3.3V)VCC 6
DQ5 7
DQ6 8
DQ7 9
DQ8 10
44 VSS(0V)
43 DQ16
42 DQ15
41 DQ14
40 DQ13
39 VSS(0V)
38 DQ12
37 DQ11
36 DQ10
35 DQ9
NC 13
NC 14
W 15
RAS 16
NC 17
A0 18
A1 19
A2 20
A3 21
(3.3V)VCC 22
32 NC
31 LCAS
30 UCAS
29 OE
28 A8
27 A7
26 A6
25 A5
24 A4
23 VSS(0V)
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION




M5M4V4265CTP-5 pdf, 반도체, 판매, 대치품
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70˚C, VCC=3.3±0.3V, VSS=0V, unless otherwise noted)
Symbol
CI (A)
CI (CLK)
CI / O
Parameter
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Test conditions
VI=VSS
f=1MHz
VI=25mVrms
Limits
Min Typ Max
5
7
7
Unit
pF
pF
pF
SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOEA
tOHC
tOHR
tCLZ
tOEZ
tWEZ
tOFF
tREZ
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
(Note 13)
(Note 7)
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
M5M4V4265C-5,-5S
Min Max
13
50
25
28
13
5
5
5
13
13
13
13
Limits
M5M4V4265C-6,-6S
Min Max
15
60
30
33
15
5
5
5
15
15
15
15
M5M4V4265C-7,-7S
Min Max
20
70
35
38
20
5
5
5
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6 : An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are
2.0V(VOH) and 0.8V(VOL).
8 : Assumes that tRCDtRCD(max) and tASCtASC(max) and tCPtCP(max).
9 : Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC
will increase by amount that tRCD exceeds the value shown.
10 : Assumes that tRADtRAD(max) and tASCtASC(max).
11 : Assumes that tCPtCP(max) and tASCtASC(max).
12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT±5µA ) and is not
reference to VOH(min) or VOL(max).
13 : Output is disabled after both RAS and CAS go to high.
4 M5M4V4265CJ,TP-5,-5S:under development

4페이지










M5M4V4265CTP-5 전자부품, 판매, 대치품
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W) (Note 25)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Min Max Min Max Min Max
tHPC Hyper page mode read/write cycle time
(Note 26) 20
25
30
tHPRWC Hyper page mode read write/read modify write cycle time
57
66
79
tDOH
Output hold time from CAS low
555
tRAS RAS low pulse width for read or write cycle (Note 27) 65 100000 77 100000 92 100000
tCP CAS high pulse width
(Note 28) 8 13
10 16
10 16
tCPRH
RAS hold time after CAS precharge
28 33 38
tCPWD
Delay time, CAS precharge to W low
(Note 24) 43
50
60
tCHOL
Hold time to maintain the data Hi-Z until CAS access
7
7
7
tOEPE
OE pulse width (Hi-Z control)
777
tWPE
W pulse width (Hi-Z control)
777
tHCWD
Delay time, CAS low to W low after read
28 32 42
tHAWD
Delay time, Address to W low after read
40 47 57
tHPWD
Delay time, CAS precharge to W low after read
43 50 60
tHCOD
Delay time, CAS low to OE high after read
13 15 20
tHAOD
Delay time, Address to OE high after read
25 30 35
tHPOD
Delay time, CAS precharge to OE high after read
28 33 38
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle.
Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode.
Note 27 : tRAS(min) is specified as two cycles of CAS input are performed.
Note 28 : tCP(max) is specified as a reference point only.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CAS before RAS Refresh Cycle (Note 29)
Limits
Symbol
Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Min Max Min Max Min Max
tCSR CAS setup time before RAS low
5 55
tCHR
tCAS
CAS hold time after RAS low
CAS low pulse width
10 10 15
17 17 22
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Unit
ns
ns
ns
Self Refresh Cycle * (Note 30)
Symbol
Parameter
tRASS
tRPS
tCHS
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
M5M4V4265C-5,-5S
Min Max
100
90
-50
Limits
M5M4V4265C-6,-6S
Min Max
100
110
-50
M5M4V4265C-7,-7S
Min Max
100
130
-50
Unit
µs
ns
ns
7
M5M4V4265CJ,TP-5,-5S:under development

7페이지


구       성 총 30 페이지수
다운로드[ M5M4V4265CTP-5.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
M5M4V4265CTP-5

EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Mitsubishi
Mitsubishi
M5M4V4265CTP-5S

EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM

Mitsubishi
Mitsubishi

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵