M5M4V64S20ATP-10L Datasheet PDF - Mitsubishi
| Part Number | M5M4V64S20ATP-10L | |
| Description | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM | |
| Manufacturers | Mitsubishi | |
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SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Some of contents are subject to change without notice.
DESCRIPTION
The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
Synchronous DRAM, with LVTTL interface. All inputs and
outputs are referenced to the rising edge of CLK. The
M5M4V64S20ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz /100MHz
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/Full Page (programmable)
- Burst type- sequential / interleave (programmable)
- Column access - random
- Burst Write / Single Write (programmable)
- Auto precharge / All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
M5M4V64S30ATP-8A
M5M4V64S30ATP-8
M5M4V64S30ATP-10
Max.
Frequency
125MHz
100MHz
100MHz
CLK Access
Time
6ns
6ns
8ns
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
Vdd
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
PIN CONFIGURATION
(TOP VIEW)
1 54 Vss
2 53 NC
3 52 VssQ
4 51 NC
5 50 DQ3
6 49 VddQ
7 48 NC
8 47 NC
9 46 VssQ
10 45 NC
11 44 DQ2
12 43 VddQ
13 42 NC
14 41 Vss
15 40 NC
16 39 DQM
17 38 CLK
18 37 CKE
19 36 NC
20 35 A11
21 34 A9
22 33 A8
23 32 A7
24 31 A6
25 30 A5
26 29 A4
27 28 Vss
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
1
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SDRAM (Rev.1.3)
Mar98
MITSUBISHI LSIs
M5M4V64S20ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
MNEMONIC
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with Auto-
Precharge
Column Address Entry
& Read
Column Address Entry
& Read with Auto-
Precharge
Auto-Refresh
Self-Refresh Entry
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TBST
MRS
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
CKE
n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
/CS /RAS /CAS /WE BA0,1 A11
HX XXXX
LHHHXX
L L HHVV
L L HLVX
L L H L XX
LHL LVX
LHL LVX
LHL HVX
LHL HVX
L L L HXX
L L L HXX
HX XXXX
LHHHXX
L HH LXX
LLLLLL
A10 A0-9
XX
XX
VV
LX
HX
LV
HV
LV
HV
XX
XX
XX
XX
XX
L V*1
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for M5M4V64S20ATP-10L electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ M5M4V64S20ATP-10L.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| M5M4V64S20ATP-10 | The function is 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM. Mitsubishi | |
| M5M4V64S20ATP-10L | The function is 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM. Mitsubishi | |
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