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M5M4V64S20ATP-12 데이터시트 PDF




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부품번호 M5M4V64S20ATP-12 기능
기능 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
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M5M4V64S20ATP-12 데이터시트, 핀배열, 회로
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
PIN CONFIGURATION
(TOP VIEW)
The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
Synchronous DRAM, with LVTTL interface. All inputs and
Vdd 1
NC 2
outputs are referenced to the rising edge of CLK. The
VddQ 3
NC 4
54 Vss
53 NC
52 VssQ
51 NC
M5M4V64S20ATP achieves very high speed data rate up to
125MHz, and is suitable for main memory or graphic memory
in computer systems.
DQ0
VssQ
NC
NC
VddQ
NC
5
6
7
8
9
10
50 DQ3
49 VddQ
48 NC
47 NC
46 VssQ
45 NC
FEATURES
- Single 3.3v±0.3v power supply
- Clock frequency 125MHz / 100MHz / 83MHz
DQ1
VssQ
NC
Vdd
NC
/WE
11
12
13
14
15
16
44 DQ2
43 VddQ
42 NC
41 Vss
40 NC (Vref)
39 DQM
- Fully synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8 (programmable)
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
17
18
19
20
21
22
23
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
- Burst type- sequential / interleave (programmable)
- Column access - random
- Auto precharge / All bank precharge controlled by A10
A1 24
A2 25
A3 26
Vdd 27
31 A6
30 A5
29 A4
28 Vss
- Auto refresh and Self refresh
- 4096 refresh cycles /64ms
- Column address A0-A9
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with
0.8mm lead pitch
M5M4V64S20ATP-8
M5M4V64S20ATP-10
M5M4V64S20ATP-12
Max.
Frequency
125MHz
100MHz
83MHz
CLK Access
Time
6ns
8ns
8ns
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
1




M5M4V64S20ATP-12 pdf, 반도체, 판매, 대치품
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
BASIC FUNCTIONS
The M5M4V64S20ATP provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3
signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.
To know the detailed definition of commands, please see the command truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
define basic commands
Refresh Option @refresh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge,
READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is
set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-
precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read /
write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated inter-
nally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
4

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M5M4V64S20ATP-12 전자부품, 판매, 대치품
SDRAM (Rev.0.2)
Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State /CS /RAS /CAS /WE Address
WRITE
H X X XX
L H H HX
L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
READ with H X X X X
AUTO
L H H HX
PRECHARGE L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
Op-Code,
LLLL
Mode-Add
WRITE with
H
X
X
XX
AUTO
L H H HX
PRECHARGE L H H L BA
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA
L L H L BA, A10
L L L HX
L L L L Op-Code,
Mode-Add
Command
Action
DESEL NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TBST
Terminate Burst
Terminate Burst, Latch CA,
READ / READA Begin Read, Determine Auto-
Precharge*3
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge*3
ACT
Bank Active / ILLEGAL*2
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TBST
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
DESEL NOP (Continue Burst to END)
NOP
NOP (Continue Burst to END)
TBST
ILLEGAL
READ / READA ILLEGAL
WRITE /
WRITEA
ILLEGAL
ACT
Bank Active / ILLEGAL*2
PRE / PREA ILLEGAL*2
REFA
ILLEGAL
MRS
ILLEGAL
MITSUBISHI ELECTRIC
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