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M5M5V32R16VP-12 데이터시트 PDF




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부품번호 M5M5V32R16VP-12 기능
기능 524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
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M5M5V32R16VP-12 데이터시트, 핀배열, 회로
1997.01.22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
The M5M5V32R16 is a family of 32768-word by 16-bit
static RAMs, fabricated with the high performance CMOS
process and designed for high speed application. These
devices operate on a single 3.3V supply, and are directly
TTL compatible.
They include a power down feature as well. In write
and read cycles, the lower and upper bytes are able
to be controled either togethe or separately by /LB
and /UB.
FEATURES
Fast access time M5M5V32R16J,TP-10 10ns(max)
M5M5V32R16J,TP-12 12ns(max)
M5M5V32R16J,TP-15 15ns(max)
Low power dissipation Active
297mW(typ)
Stand by
0.33mW(typ)
Single +3.3V power supply
Fully static operation : No clocks, No refresh
Common data I/O
Easy memory expansion by /S
Three-state outputs : OR-tie capability
OE prevents data contention in the I/O bus
Directly TTL compatible : All inputs and outputs
Separate control of lower and upper bytes by /LB and /UB
PIN CONFIGURATION (TOP VIEW)
N.C
A3
ADDRESS
INPUTS
A2
A1
CHIP
SELECT
INPUTS
DATA
INPUTS/
OUTPUTS
A0
/S
DQ1
DQ2
DQ3
DQ4
(3.3V) Vcc
(0V) GND
DATA
INPUTS/
OUTPUTS
DQ5
DQ6
DQ7
WRITE
CONTROL
INPUT
DQ8
/W
A14
ADDRESS
INPUTS
A13
A12
A11
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 A4
43
A5
ADDRESS
INPUTS
42 A6
41
/OE
OUTPUT
ENABLE
40
/UB BYTE
CONTROL
39 /LB INPUTS
38 DQ16
35
DQ15
DATA
INPUTS/
36 DQ14 OUTPUTS
35 DQ13
34 GND (0V)
33 Vcc (3.3V)
32 DQ12
31
DQ11
DATA
INPUTS/
30 DQ10 OUTPUTS
29 DQ9
28 NC
27 A7
26 A8 ADDRESS
25 A9
INPUTS
24 A10
23 NC
Outline 44P0K(J)
44P3W-H(TP)
APPLICATION
High-speed memory system
FUNCTION
The operation mode of the M5M5V32R16 is
determined by a combination of the device control
inputs /S, /W, /OE, /LB, and /UB. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level /W
overlaps with low level /LB and/or low level /UB and low
level /S. The address must be set-up before write cycle
and must be stable during the entire cycle.
The data is latched into a cell on the traling edge of
/W, /LB, /UB or /S, whichever occurs first, requiring the
set-up and hold time relative to these edge to be
maintained. The output enable input /OE directly
controls the output stage. Setting the /OE at a high
level, the output stage is in a high impedance state, and
the data bus contention problem in the write cycle is
eliminated.
A read cycle is excuted by setting W at a high level
and /OE at a low level while /LB and/or /UB and /S are
in an active state. (/LB and/or /UB=L, /S=L)
PACKAGE
M5M5V32R16J : 44pin 400mil SOJ
M5M5V32R16VP: 44pin 400mil TSOP(II)
When setting /LB at a high level and other pins are in
an active state, upper-Byte are in a selectable mode
in which both reading and writing are enable, and
lower-Byte are in a non-selectable mode. And when
setting /UB at a high level and other pins are in an
active state, lower-Byte are in a selectable mode in
which both reading and writing are enable, and
upper-Byte are in a non-selectable mode.
When setting /LB and /UB at a high level or /S at high
level, the chip is in a non-selectable mode in which
both reading and writing are disabled. In this mode,
the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory
expansion by /LB, /UB and /S.
Signal-/S controls the power-down feature. When /S
goes high, power dissapation is reduced extremely.
The access time from /S is equivalent to the address
access time.
MITSUBISHI
ELECTRIC
1




M5M5V32R16VP-12 pdf, 반도체, 판매, 대치품
MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Symbol
Parameter
tCR
ta (A)
ta (S)
ta (OE)
ta (B)
tdis (S)
tdis (OE)
tdis (B)
ten (S)
ten (OE)
ten (B)
tv (A)
tPU
tPD
Read cycle time
Address access time
Chip select access time
Output enable access time
/LB,/UB access time
Output disable time after /S high
Output disable time after /OE high
Output disable time after /LB,/UB high
Output enable time after /S low
Output enable time after /OE low
Output enable time after /LB,/UB low
Data valid time after address change
Power-up time after chip selection
Power down time after chip selection
Limits
M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit
Min Max Min Max Min Max
10
10
10
5
5
05
05
05
4
3
3
4
0
10
12
12
12
6
6
06
06
06
4
3
3
4
0
12
15 ns
15 ns
15 ns
7 ns
7 ns
0 7 ns
0 7 ns
0 7 ns
4 ns
3 ns
3 ns
4 ns
0 ns
15 ns
Write cycle
Symbol
Parameter
tCW
tw(W)
tsu (B)
tsu (A)1
tsu (A)2
tsu (S)
tsu (D)
th(D)
trec(W)
tdis (W)
tdis (OE)
ten (W)
ten (OE)
ten (B)
tsu(A-WH)
tsu(A-SH)
tsu (A-BH)
Write cycle time
Write pulse width
/LB,/UB setup time
Address setup time(/W)
Address setup time(/S)
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time after /W low
Output disable time after /OE high
Output enable time after /W high
Output enable time after /OE low
Output enable time after /LB,/UB low
Address to /W High
Address to /S High
Address to /LB,/UB High
Limits
M5M5V32R16 -10 M5M5V32R16 -12 M5M5V32R16 -15 Unit
Min Max Min Max Min Max
10 12 15 ns
9 10 12 ns
9 10 12 ns
0 0 0 ns
0 0 0 ns
9 10 12 ns
5 6 7 ns
0 0 0 ns
0 0 0 ns
0 5 0 6 0 7 ns
0 5 0 6 0 7 ns
0 0 0 ns
0 0 0 ns
0 0 0 ns
9 10 12 ns
9 10 12 ns
9 10 12 ns
MITSUBISHI
ELECTRIC
4

4페이지










M5M5V32R16VP-12 전자부품, 판매, 대치품
MITSUBISHI LSIs
M5M5V32R16J,TP-10,-12,-15
524288-BIT (32768-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle(/S control)
A 0~14
/S
/W
/LB,/UB
VIH
VIL
tsu (A)
VIH
VIL
VIH
VIL
(Note7)
VIH
VIL
(Note7)
DQ1~16
(Input Data)
DQ1~16
(Output Data)
VIH
VIL
VOH
VOL
(Note5)
ten (S)
t CW
tsu (S)
trec (W)
tw (W)
tsu (B)
(Note7)
tsu(D) th(D)
DATA STABLE
tdis(W) (Note5)
Hi-Z
(Note9)
(Note7)
Write cycle(/LB,/UB control)
A 0~14
/S
/W
/LB,/UB
VIH
VIL
VIH
VIL
(Note7)
VIH
VIL
(Note7)
tsu (A)
VIH
VIL
DQ1~16
(iInput Data)
DQ1~16
(Output Data)
VIH
VIL
(Note5)
VOH
ten (B)
VOL
t CW
tsu (S)
tw (W)
tsu (B)
(Note7)
trec (W)
(Note7)
tsu(D) th (D)
DATA STABLE
tdis (W) (Note5)
Hi-Z
(Note9)
MITSUBISHI
ELECTRIC
7

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