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M5M5V416BTP 데이터시트 PDF




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부품번호 M5M5V416BTP 기능
기능 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
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M5M5V416BTP 데이터시트, 핀배열, 회로
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5V416B is a f amily of low v oltage 4-Mbit static RAMs
organized as 262,144-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
The M5M5V416B is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V416BTP,RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V416BTP (normal lead bend ty pe package)
, M5M5V416BRT (rev erse lead bend ty pe package) , both ty pes
are v ery easy t o design a printed circuit board.
From the point of operating temperature, the f amily is div ided into
three v ersions; "Standard", "W-v ersion", and "I-v ersion". Those are
summarized in the part name table below.
Version,
Operating
Part name
temperature
M5M5V416BTP , RT -70L
M5M5V416BTP , RT -85L
Standard M5M5V416BTP , RT -10L
0 ~ +70°C M5M5V416BTP , RT -70H
M5M5V416BTP , RT -85H
M5M5V416BTP , RT -10H
M5M5V416BTP , RT -70LW
M5M5V416BTP , RT -85LW
W-v ersion M5M5V416BTP , RT -10LW
-20 ~ +85°C M5M5V416BTP , RT -70HW
M5M5V416BTP , RT -85HW
M5M5V416BTP , RT -10HW
M5M5V416BTP , RT -70LI
M5M5V416BTP , RT -85LI
I-v ersion M5M5V416BTP , RT -10LI
-40 ~ +85°C M5M5V416BTP , RT -70HI
M5M5V416BTP , RT -85HI
M5M5V416BTP , RT -10HI
PIN CONFIGURATION
Power
Supply
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
Access time
max.
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
70ns
85ns
100ns
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S1, S2, BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology : 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
Stand-by c urrent Icc(PD), Vcc=3.0V
Activ e
ty pical *
Ratings (max.)
current
Icc1
25°C 40°C 25°C 40°C 70°C 85°C (3.0V, ty p.)
--- --- --- --- 20µA ---
0.3µA 1µA 1µA 3µA 10µA ---
--- ---
0.3µA 1µA
--- ---
--- --- 20µA 40µA
1µA 3µA 10µA 20µA
--- --- 20µA 40µA
40mA
(10MHz)
5mA
(1MHz)
0.3µA 1µA 1µA 3µA 10µA 20µA
* "ty pical" parameter is sampled, not 100% tested.
A4
A3
A2
A1
A0
S1
DQ1
DQ2
DQ3
DQ4
Vcc
GND
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44P3W-H
44 A5
A5 44
43 A6
A6 43
42 A7
A7 42
41 OE
OE 41
40 BC2
BC2 40
39 BC1
BC1 39
38 DQ16 DQ16 38
37 DQ15 DQ15 37
36 DQ14 DQ14 36
35 DQ13 DQ13 35
34 GND
GND
34
33 Vcc
Vcc 33
32 DQ12 DQ12 32
31 DQ11 DQ11 31
30 DQ10 DQ10 30
29 DQ9
DQ9 29
28 S2
S2 28
27 A8
A8 27
26 A9
A9 26
25 A10
A10 25
24 A11
A11 24
23 A17
A17 23
1 A4
2 A3
3 A2
4 A1
Pin
Function
5 A0
6 S1
A0 ~ A17 Address input
7 DQ1 DQ1 ~ DQ16 Data input / output
8 DQ2
9 DQ3
S1 Chip select input 1
10 DQ4
11 Vcc
S2 Chip select input 2
12 GND
13 DQ5
14 DQ6
W Write control input
OE Output enable input
15 DQ7
16 DQ8
BC1
Lower By te (DQ1 ~ 8)
17 WE
18 A15
19 A14
BC2
Vcc
Upper By te (DQ9 ~ 16)
Power supply
20 A13
21 A12
GND
Ground supply
22 A16
Outline: 44P3W-H/J
44P3W-J
NC: No Connection
MITSUBISHI ELECTRIC
1




M5M5V416BTP pdf, 반도체, 판매, 대치품
revision-P04, ' 98.12.16
MITSUBISHI LSIs
M5M5V416BTP,RT
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Supply v oltage
2.7V~3.6V
Input pulse
V IH= 2 . 4 V , V IL= 0 . 4 V
Input rise time and f all time 5ns
Ref erence lev el
Output loads
V OH=V OL= 1 . 5 V
Transition is measured ±500mV f rom
steady state voltage.(f or ten,t dis)
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
1TTL
DQ
CL
Including scope and
jig capacitance
Fig.1 Output load
(2) READ CYCLE
Symbol
Parameter
t CR
ta(A)
ta(S1)
ta(S2)
ta(BC1)
ta(BC2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S1)
ten(S2)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
Read cy cle time
Address access time
Chip select 1 access time
Chip select 2 access time
By te control 1 access time
By te control 2 access time
Output enable access time
Output disable time af t er S1 high
Output disable time af t er S2 low
Output disable time af t er BC1 high
Output disable time af t er BC2 high
Output disable time af t er OE high
Output enable time af ter S1 low
Output enable time af ter S2 high
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
70L,70H,70LW
70HW,70LI,70HI
Min Max
70
70
70
70
70
70
35
25
25
25
25
25
10
10
10
10
10
Limits
85L,85H,85LW
85HW,85LI,85HI
Min Max
85
85
85
85
85
85
45
30
30
30
30
30
10
10
10
10
5
10
10L,10H,10LW
10HW,10LI,10HI Units
Min Max
100 ns
100 ns
100 ns
100 ns
100 ns
100 ns
50 ns
35 ns
35 ns
35 ns
35 ns
35 ns
10 ns
10 ns
10 ns
10 ns
5 ns
10 ns
(3) WRITE CYCLE
Symbol
Parameter
tCW
tw(W)
Write cy cle time
Write pulse width
tsu(A)
Address setup time
tsu(A-WH) Address setup time with respect to W
tsu(BC1) By te control 1 setup time
tsu(BC2) By te control 2 setup time
tsu(S1) Chip select 1 setup time
tsu(S2) Chip select 2 setup time
tsu(D)
Data setup time
th(D)
Data hold time
trec(W) Write recov ery time
tdis(W) Output disable time f rom W low
tdis(OE) Output disable time f rom OE high
ten(W) Output enable time f rom W high
ten(OE) Output enable time f rom OE low
Limits
70L,70H,70LW 85L,85H,85LW
70HW,70LI,70HI 85HW,85LI,85HI
Min Max Min Max
70 85
55 60
00
65 70
65 70
65 70
65 70
65 70
35 35
00
00
25
25
55
55
30
30
10L,10H,10LW
10HW,10LI,10HI
Min Max
100
75
0
85
85
85
85
85
40
0
0
35
35
5
5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MITSUBISHI ELECTRIC
4

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M5M5V416BTP 전자부품, 판매, 대치품
revision-P04, ' 98.12.16
M5M5V416BTP,RT
Write cycle (S1 control mode)
A 0~17
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change
4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
tCW
BC1 ,BC2
S1
(Note3)
tsu (A)
tsu (S1)
trec (W)
(Note3)
S2
(Note3)
(Note5)
W
(Note3)
DQ1~16
Write cycle (S2 control mode)
A 0~17
BC1,BC2
S1
(Note3)
tsu (A)
(Note4)
tsu (D) th (D)
DATA IN
STABLE
tCW
tsu (S2)
trec (W)
(Note3)
(Note3)
(Note3)
S2
W
DQ1~16
(Note3)
(Note5)
(Note3)
(Note4)
tsu (D) th (D)
DATA IN
STABLE
(Note3)
(Note3)
MITSUBISHI ELECTRIC
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부품번호상세설명 및 기능제조사
M5M5V416BTP

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

Mitsubishi
Mitsubishi

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